User guide

Embedded Trace Macrocell
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 10-21
ID072410 Non-Confidential
Table 10-15 shows the ITMISCIN bit assignments.
10.3.12 Integration Test Trigger Out, ITTRIGOUT
The ITMISCIN characteristics are:
Purpose Integration test.
Usage constraints You must set bit [0] of ETMITCTRL to use this register.
Configurations This register is only available if the processor is configured to use the
ETM.
Attributes See the register summary in Table 10-6 on page 10-9.
Figure 10-11 shows the ITTRIGOUT bit assignments.
Figure 10-11 ITTRIGOUT bit assignments
Table 10-16 shows the ITTRIGOUT bit assignments.
10.3.13 ETM Integration Test ATB Control 2, ETM_ITATBCTR2
The ETM_ITATBCTR2 characteristics are:
Purpose Integration test.
Usage constraints You must set bit [0] of ETMITCTRL to use this register.
Configurations This register is only available if the processor is configured to use the
ETM.
Attributes See the register summary in Table 10-6 on page 10-9.
Figure 10-12 on page 10-22 shows the ETM_ITATBCTR2 bit assignments.
Table 10-15 ITMISCIN bit assignments
Bits Name Function
[31:5] - Reserved.
[4] COREHALT A read of this bit returns the value of the COREHALT input pin.
[3:2] - Reserved.
[1:0] EXTIN[1:0] A read of these bits returns the value of the EXTIN[1:0] input pins.
Reserved
31 10
TRIGGER output value
Table 10-16 ITTRIGOUT bit assignments
Bits Name Function
[31:1] - Reserved
[0] TRIGGER output value A write to this bit sets the TRIGGER output.