User guide

Embedded Trace Macrocell
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 10-20
ID072410 Non-Confidential
Usage constraints There are no usage constraints.
Configurations This register is only available if the processor is configured to use an ETM.
Attributes See the register summary in Table 10-6 on page 10-9.
Figure 10-9 shows the ETMPDSR bit assignments.
Figure 10-9 ETMPDSR bit assignments
Table 10-14 shows the ETMPDSR bit assignments.
10.3.11 Integration Test Miscellaneous Inputs, ITMISCIN
The ITMISCIN characteristics are:
Purpose Integration test.
Usage constraints There are no usage constraints.
Configurations This register is only available if the processor is configured to use the
ETM.
Attributes See the register summary in Table 10-6 on page 10-9.
Figure 10-10 shows the ITMISCIN bit assignments.
Figure 10-10 ITMISCIN bit assignments
Reserved, RAZ
31 0
1
ETM powered up
Table 10-14 ETMPDSR bit assignments
Bits Name Function
[31:1] - Reserved, Read-As-Zero.
[0] ETM powered up The value of this bit indicates whether you can access the ETM Trace Registers. The value of this bit is
always 1, indicating that the ETM Trace Registers can be accessed.
Reserved
31 543210
COREHALT
Reserved
EXTIN[1:0]