User guide
Embedded Trace Macrocell
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 10-16
ID072410 Non-Confidential
10.3.6 TraceEnable Control 1 Register, ETMTECR1
The ETMTECR1 characteristics are:
Purpose Enables the start/stop logic used for trace enable.
Usage constraints There are no usage constraints.
Configurations This register is only available if the processor is configured to use the
ETM.
Attributes See the register summary in Table 10-6 on page 10-9.
Figure 10-5 shows the ETMTECR1 bit assignments.
Figure 10-5 ETMTECR1 bit assignments
Table 10-10 shows the ETMTECR1 bit assignments.
[10] Port size supported This bit reads as 1 if the currently selected port size is supported. This has no effect on the
TPIU trace port.
[9] Maximum port size [3] Maximum ETM port size bit [3]. This bit is used in conjunction with bits [2:0]. Its value is 0.
This has no effect on the TPIU trace port.
[8] FIFOFULL supported The value of this bit is 1, indicating that FIFOFULL is supported. This bit is used in
conjunction with bit [23] of the ETMCCR.
[7:4] - Reserved, Read-As-Zero.
[3] - Reserved, Read-As-One.
[2:0] Maximum port size [2:0] Maximum ETM port size bits [2:0]. These bits are used in conjunction with bit [9]. The value
of these bits is
0b001
.
Table 10-9 ETMSCR bit assignments (continued)
Bits Name Function
Reserved
31 0
Reserved
26 25 24
Trace control enable
Table 10-10 ETMTECR1 bit assignments
Bits Name Function
[31:26] - Reserved.
[25] Trace control enable Trace start/stop enable. The possible values of this bit are:
0 Tracing is unaffected by the trace start/stop logic.
1 Tracing is controlled by the trace on and off addresses configured for the trace
start/stop logic.
The trace start/stop resource, resource
0x5F
, is unaffected by the value of this bit.
[24:0] - Reserved.