Cortex -M3 ™ Revision r2p1 Technical Reference Manual Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Cortex-M3 Technical Reference Manual Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. Release Information The following changes have been made to this book.
Contents Cortex-M3 Technical Reference Manual Preface About this book ............................................................................................................ x Feedback .................................................................................................................. xiii Chapter 1 Introduction 1.1 1.2 1.3 1.4 1.5 1.6 Chapter 2 About the functions .................................................................................................. 2-2 Interfaces ......
Contents Chapter 4 System Control 4.1 4.2 4.3 Chapter 5 About system control ............................................................................................... 4-2 Register summary .................................................................................................... 4-3 Register descriptions ............................................................................................... 4-5 Memory Protection Unit 5.1 5.2 5.3 Chapter 6 About the MPU .........................
List of Tables Cortex-M3 Technical Reference Manual Table 1-1 Table 3-1 Table 3-2 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 5-1 Table 6-1 Table 6-2 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 Table 7-6 Table 7-7 Table 8-1 Table 9-1 Table 9-2 Table 10-1 Table 10-2 Table 10-3 Table 10-4 Table 10-5 Table 10-6 Table 10-7 Table 10-8 Table 10-9 ARM DDI 0337I ID072410 Change History .........................................................................................................................
List of Tables Table 10-10 Table 10-11 Table 10-12 Table 10-13 Table 10-14 Table 10-15 Table 10-16 Table 10-17 Table 10-18 Table 11-1 Table 11-2 Table 11-3 Table 11-4 Table 11-5 Table 11-6 Table 11-7 Table 11-8 Table 11-9 Table 11-10 Table 11-11 Table A-1 Table A-2 Table A-3 Table A-4 ARM DDI 0337I ID072410 ETMTECR1 bit assignments ................................................................................................... 10-16 ETMIDR bit assignments ..............................................
List of Figures Cortex-M3 Technical Reference Manual Figure 2-1 Figure 3-1 Figure 3-2 Figure 3-3 Figure 4-1 Figure 4-2 Figure 4-3 Figure 6-1 Figure 7-1 Figure 7-2 Figure 9-1 Figure 10-1 Figure 10-2 Figure 10-3 Figure 10-4 Figure 10-5 Figure 10-6 Figure 10-7 Figure 10-8 Figure 10-9 Figure 10-10 Figure 10-11 Figure 10-12 Figure 10-13 Figure 11-1 Figure 11-2 Figure 11-3 Figure 11-4 Figure 11-5 Figure 11-6 ARM DDI 0337I ID072410 Cortex-M3 block diagram .........................................................
List of Figures Figure 11-7 Figure 11-8 Figure 11-9 Figure 11-10 Figure 11-11 Figure 11-12 ARM DDI 0337I ID072410 ITATBCTR2 bit assignments .................................................................................................... 11-9 Integration ITM Data bit assignments ..................................................................................... 11-10 ITATBCTR0 bit assignments ..................................................................................................
Preface This preface introduces the Cortex-M3 Technical Reference Manual (TRM). It contains the following sections: • About this book on page x • Feedback on page xiii. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Preface About this book This book is for the Cortex-M3 processor. Product revision status The rnpn identifier indicates the revision status of the product described in this manual, where: rn Identifies the major revision of the product. pn Identifies the minor revision or modification status of the product.
Preface Appendix A Revisions Read this for a description of the technical changes between released issues of this book. Glossary Read this for definitions of terms used in this book. Conventions Conventions that this book can use are described in: • Typographical Typographical The typographical conventions are: italic Highlights important notes, introduces special terminology, denotes internal cross-references, and citations. bold Highlights interface elements, such as menu names.
Preface Other publications This section lists relevant documents published by third parties: • IEEE Standard Test Access Port and Boundary-Scan Architecture 1149.1-2001 (JTAG). ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Preface Feedback ARM welcomes feedback on this product and its documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier and give: • The product name. • The product revision or version. • An explanation with as much information as you can provide. Include symptoms and diagnostic procedures if appropriate. Feedback on this manual If you have comments on content then send e-mail to errata@arm.com.
Chapter 1 Introduction This chapter introduces the processor and instruction set. It contains the following sections: • About the processor on page 1-2 • Features on page 1-3 • Interfaces on page 1-4 • Configurable options on page 1-5 • Product documentation on page 1-6 • Product revisions on page 1-9. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Introduction 1.1 About the processor The Cortex-M3 is a low-power processor that features low gate count, low interrupt latency, and low-cost debug. It is intended for deeply embedded applications that require optimal interrupt response features. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Introduction 1.2 Features The Cortex-M3 processor incorporates: ARM DDI 0337I ID072410 • a processor core • a Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to achieve low latency interrupt processing • multiple high-performance bus interfaces • a low-cost debug solution with the optional ability to: — implement breakpoints and code patches — implement watchpoints, tracing, and system profiling — support printf() style debugging.
Introduction 1.3 Interfaces The processor has the following external interfaces: • multiple memory and device bus interfaces • ETM interface • trace port interface • debug port interface • if the implementation includes an ETM, a Cross Trigger Interface (CTI). ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Introduction 1.4 Configurable options You can configure your Cortex-M3 implementation to include the following optional components: Table 1-1 Optional implementation components Component Description MPU See Chapter 5 Memory Protection Unit FPB Flash Patch and Breakpoint Unit. See Chapter 7 Debug DWT See Chapter 8 Data Watchpoint and Trace Unit ITM See Chapter 9 Instrumentation Trace Macrocell Unit ETM See Chapter 10 Embedded Trace Macrocell AHB-AP Advanced High-performance Bus Access Port.
Introduction 1.5 Product documentation This section describes the processor books, how they relate to the design flow, and the relevant architectural standards and protocols. See Additional reading on page xi for more information about the books described in this section. 1.5.
Introduction • each top-level section in this reference material might correspond to a chapter in the User Guide. However, ARM partners can organize this material in any way, subject to the conditions of the licence agreement under which ARM supplied the material. 1.5.2 Design Flow The processor is delivered as synthesizable RTL.
Introduction • • • Bus architecture Debug Embedded Trace Macrocell. This book complements architecture reference manuals, architecture specifications, protocol specifications, and relevant external standards. It does not duplicate information from these sources. ARM architecture The processor implements the ARMv7-M architecture profile. See the ARMv7-M Architecture Reference Manual. For more information about architectural compliance, see Architecture and protocol information on page 1-9.
Introduction 1.6 Product revisions This section summarizes the differences in functionality between the different releases of this processor: • Differences in functionality between r0p0 and r1p0 • Differences in functionality between r1p0 and r1p1 • Differences in functionality between r1p1 and r2p0 on page 1-10 • Differences in functionality between r2p0 and r2p1 on page 1-10. 1.6.1 Differences in functionality between r0p0 and r1p0 In summary, the differences in functionality include: 1.6.
Introduction • 1.6.3 Errata fixes to the r1p0 release. Differences in functionality between r1p1 and r2p0 In summary, the differences in functionality include: 1.6.4 • Implementation time options have been added to select between different levels of debug and trace support. This has replaced the previous TIEOFF_FPBEN and TIEOFF_TRCENA options. • New implementation option to enable the resetting of all registers within the processor.
Introduction ARM DDI 0337I ID072410 • DBGEN input added as master debug enable. If de-asserted then debug is disabled. • ETM upgraded from ARM ETM architecture v3.4 to 3.5 to include global time-stamping. • The Vector Table Offset Register located at address 0xE000ED08 has been increased by two bits from 29:7 to 31:7. • ROM table identification registers have been updated. See Cortex-M3 ROM table identification and entries on page 7-3. • Verilog file and module names have been modified.
Chapter 2 Functional Description This chapter introduces the processor and its external interfaces. It contains the following sections: • About the functions on page 2-2 • Interfaces on page 2-4. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Functional Description 2.1 About the functions Figure 2-1 shows the structure of the Cortex-M3 processor.
Functional Description • • • • ARM DDI 0337I ID072410 Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to achieve low latency interrupt processing. Features include: — External interrupts, configurable from 1 to 240. — Bits of priority, configurable from 3 to 8. — Dynamic reprioritization of interrupts. — Priority grouping. This enables selection of preempting interrupt levels and non preempting interrupt levels.
Functional Description 2.2 Interfaces The processor contains the following external interfaces: • Bus interfaces • ETM interface on page 2-6 • AHB Trace Macrocell interface on page 2-6 • Debug Port AHB-AP interface on page 2-6. 2.2.
Functional Description DCode memory interface Data and debug accesses to Code memory space, 0x00000000 to 0x1FFFFFFF, are performed over this 32-bit AHB-Lite bus. Core data accesses have a higher priority than debug accesses on this bus. This means that debug accesses are waited until core accesses have completed when there are simultaneous core and debug access to this bus.
Functional Description 2.2.2 • only 32-bit data accesses are supported • it is accessible from the Debug Port and the local processor, but not from any other processor in the system. ETM interface The ETM interface enables simple connection of an ETM to the processor. It provides a channel for instruction trace to the ETM. See the ARM Embedded Trace Macrocell Architecture Specification. 2.2.
Chapter 3 Programmers Model This chapter describes the processor programmers model. It contains the following sections: • About the programmers model on page 3-2 • Modes of operation and execution on page 3-3 • Instruction set summary on page 3-4 • System address map on page 3-11 • Write buffer on page 3-14 • Bit-banding on page 3-16 • Processor core register summary on page 3-18 • Exceptions on page 3-20. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Programmers Model 3.1 About the programmers model The ARMv7-M Architecture Reference Manual provides a complete description of the programmers model. This chapter gives an overview of the Cortex-M3 processor programmers model that describes the implementation-defined options. It also contains the ARMv7-M Thumb instructions the model uses, and their cycle counts for the processor.
Programmers Model 3.2 Modes of operation and execution This section briefly describes the modes of operation and execution of the Cortex-M3 processor. See the ARMv7-M Architecture Reference Manual for more information. 3.2.1 Operating modes The processor supports two modes of operation, Thread mode and Handler mode: 3.2.2 • The processor enters Thread mode on Reset, or as a result of an exception return. Privileged and Unprivileged code can run in Thread mode.
Programmers Model 3.3 Instruction set summary This section provides information on: • Cortex-M3 instructions • Load/store timings on page 3-8 • Binary compatibility with other Cortex processors on page 3-9. 3.3.1 Cortex-M3 instructions The processor implements the ARMv7-M Thumb instruction set. Table 3-1 shows the Cortex-M3 instructions and their cycle counts. The cycle counts are based on a system with zero wait states.
Programmers Model Table 3-1 Cortex-M3 instruction set summary (continued) Operation Description Assembler Cycles Subtract Subtract SUB Rd, Rn, 1 Subtract with borrow SBC Rd, Rn, 1 Reverse RSB Rd, Rn, 1 Multiply MUL Rd, Rn, Rm 1 Multiply accumulate MLA Rd, Rn, Rm 2 Multiply subtract MLS Rd, Rn, Rm 2 Long signed SMULL RdLo, RdHi, Rn, Rm 3 to 5a Long unsigned UMULL RdLo, RdHi, Rn, Rm 3 to 5a Long signed accumulate SMLAL RdLo, RdHi, Rn, Rm 4 to 7a Long unsigned
Programmers Model Table 3-1 Cortex-M3 instruction set summary (continued) Operation Description Assembler Cycles Rotate Rotate right ROR Rd, Rn, # 1 Rotate right ROR Rd, Rn, Rs 1 With extension RRX Rd, Rn 1 Count Leading zeroes CLZ Rd, Rn 1 Load Word LDR Rd, [Rn, ] 2c To PC LDR PC, [Rn, ] 2c + P Halfword LDRH Rd, [Rn, ] 2c Byte LDRB Rd, [Rn, ] 2c Signed halfword LDRSH Rd, [Rn, ] 2c Signed byte LDRSB Rd, [Rn, ] 2c User word LDRT Rd, [R
Programmers Model Table 3-1 Cortex-M3 instruction set summary (continued) Operation Description Assembler Cycles Push Push PUSH {} 1+N Push with link register PUSH {, LR} 1+N Pop POP {} 1+N Pop and return POP {, PC} 1+N+P Load exclusive LDREX Rd, [Rn, #] 2 Load exclusive half LDREXH Rd, [Rn] 2 Load exclusive byte LDREXB Rd, [Rn] 2 Store exclusive STREX Rd, Rt, [Rn, #] 2 Store exclusive half STREXH Rd, Rt, [Rn] 2 Store exclusive b
Programmers Model Table 3-1 Cortex-M3 instruction set summary (continued) Operation Description Assembler Cycles Bit field Extract unsigned UBFX Rd, Rn, #, # 1 Extract signed SBFX Rd, Rn, #, # 1 Clear BFC Rd, Rn, #, # 1 Insert BFI Rd, Rn, #, # 1 Bytes in word REV Rd, Rm 1 Bytes in both halfwords REV16 Rd, Rm 1 Signed bottom halfword REVSH Rd, Rm 1 Bits in word RBIT Rd, Rm 1 Send event SEV 1 Wait for event WFE 1+W Wait for interrupt
Programmers Model • Any load or store that generates an address dependent on the result of a proceeding data processing operation will stall the pipeline for an additional cycle whilst the register bank is updated. There is no forwarding path for this scenario. • LDR Rx,[PC,#imm] might add a cycle because of contention with the fetch unit. • TBB and TBH are also blocking operations. These are at least two cycles for the load, one cycle for the add, and three cycles for the pipeline reload.
Programmers Model • ARM DDI 0337I ID072410 configure the following fields in the CCR: — STKALIGN bit to 1 — UNALIGN_TRP bit to 1 — Leave all other bits in the CCR register as their original value. Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Programmers Model 3.4 System address map The processor contains a bus matrix that arbitrates the processor core and optional Debug Access Port (DAP) memory accesses to both the external memory system and to the internal System Control Space (SCS) and debug components. Priority is always given to the processor to ensure that any debug accesses are as non-intrusive as possible. For a zero wait state system, all debug accesses to system memory, SCS, and debug resources are completely non-intrusive.
Programmers Model Table 3-2 Memory regions (continued) Memory Map Region Peripheral bit-band Alias region. Data accesses are aliases. Instruction accesses are not aliases. External RAM Instruction fetches and data accesses are performed over the system bus. External Device Instruction fetches and data accesses are performed over the system bus. Private Peripheral Bus External and internal Private Peripheral Bus (PPB) interfaces. See Private peripheral bus.
Programmers Model • System accesses that cross into PPB space do not wrap within System space. For example, an unaligned halfword access to the last byte of System space (0xDFFFFFFF) is converted by the System interface into a byte access to 0xDFFFFFFF followed by a byte access to 0xE0000000. 0xE0000000 is not a valid address on the System bus. • System accesses that cross into Code space do not wrap within System space.
Programmers Model 3.5 Write buffer To prevent bus wait cycles from stalling the processor during data stores, buffered stores to the DCode and System buses go through a one-entry write buffer. If the write buffer is full, subsequent accesses to the bus stall until the write buffer has drained. The write buffer is only used if the bus waits the data phase of the buffered store, otherwise the transaction completes on the bus. DMB and DSB instructions wait for the write buffer to drain before completing.
Programmers Model 3.6 Exclusive monitor The Cortex-M3 processor implements a local exclusive monitor. For more information about semaphores and the local exclusive monitor, see the ARMv7M ARM Architecture Reference Manual. The local monitor within the processor has been constructed so that it does not hold any physical address, but instead treats any access as matching the address of the previous LDREX. This means that the implemented exclusives reservation granule is the entire memory address range.
Programmers Model 3.7 Bit-banding Bit-banding maps a complete word of memory onto a single bit in the bit-band region. For example, writing to one of the alias words sets or clears the corresponding bit in the bit-band region. This enables every individual bit in the bit-banding region to be directly accessible from a word-aligned address using a single LDR instruction. It also enables individual bits to be toggled without performing a read-modify-write sequence of instructions.
Programmers Model • The alias word at 0x2200001C maps to bit [7] of the bit-band byte at 0x20000000: 0x2200001C = 0x22000000 + (0*32) + 7*4.
Programmers Model 3.8 Processor core register summary The processor has the following 32-bit registers: • 13 general-purpose registers, R0-R12 • Stack Pointer (SP), R13 alias of banked registers, SP_process and SP_main • Link Register (LR), R14 • Program Counter (PC), R15 • Special-purpose Program Status Registers, (xPSR). Figure 3-3 shows the processor register set.
Programmers Model Bit [0] is always 0, so instructions are always aligned to word or halfword boundaries. See the ARMv7-M Architecture Reference Manual for more information. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Programmers Model 3.9 Exceptions The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. When handling exceptions: • All exceptions are handled in Handler mode. • Processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). • The vector is fetched in parallel to the state saving, enabling efficient interrupt entry.
Programmers Model This means that software must not use load-multiple or store-multiple instructions to access a device or access a memory region that is read-sensitive or sensitive to repeated writes. The software must not use these instructions in any case where repeated reads or writes might cause inconsistent results or unwanted side-effects.
Chapter 4 System Control This chapter describes the registers that program the processor. It contains the following sections: • About system control on page 4-2 • Register summary on page 4-3 • Register descriptions on page 4-5. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
System Control 4.1 About system control This chapter describes the registers that control the operation of the processor. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
System Control 4.2 Register summary Table 4-1 shows the system control registers.
System Control Table 4-1 System control registers (continued) Address Name Type Reset Description 0xE000ED64 ID_ISAR1 RO 0x02111000 Instruction Set Attributes Register 1 0xE000ED68 ID_ISAR2 RO 0x21112231 Instruction Set Attributes Register 2 0xE000ED6C ID_ISAR3 RO 0x01111110 Instruction Set Attributes Register 3 0xE000ED70 ID_ISAR4 RO 0x01310132 Instruction Set Attributes Register 4 0xE000ED88 CPACR RW 0x00000000 Coprocessor Access Control Register 0xE000EF00 STIR WO 0x0000
System Control 4.3 Register descriptions This section describes the system control registers whose implementation is specific to this processor. 4.3.1 Auxiliary Control Register, ACTLR The ACTLR characteristics are: Purpose Disables certain aspects of functionality within the processor. Usage Constraints There are no usage constraints. Configurations This register is available in all processor configurations. Attributes See the register summary in Table 4-1 on page 4-3.
System Control Figure 4-2 shows the CPUID bit assignments. 31 24 23 IMPLEMENTER 20 19 VARIANT 16 15 4 3 (Constant) PARTNO 0 REVISION Figure 4-2 CPUID bit assignments Table 4-3 shows the CPUID bit assignments. Table 4-3 CPUID bit assignments 4.3.
Chapter 5 Memory Protection Unit This chapter describes the processor Memory Protection Unit (MPU). It contains the following sections: • About the MPU on page 5-2 • MPU functional description on page 5-3 • MPU programmers model on page 5-4. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Memory Protection Unit 5.1 About the MPU The MPU is an optional component for memory protection. The processor supports the standard ARMv7 Protected Memory System Architecture model. The MPU provides full support for: • protection regions • overlapping protection regions, with ascending region priority: — 7 = highest priority — 0 = lowest priority. • access permissions • exporting memory attributes to the system.
Memory Protection Unit 5.2 MPU functional description The attribute bits, TEX, C, B, AP, and XN, of the Region Access Control Register control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then a permission fault is raised. For more information, see the ARMv7-M Architecture Reference Manual. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Memory Protection Unit 5.3 MPU programmers model Table 5-5 shows the MPU registers. These registers are described in the ARMv7-M Architecture Reference Manual.
Chapter 6 Nested Vectored Interrupt Controller This chapter describes the Nested Vectored Interrupt Controller (NVIC). It contains the following sections: • About the NVIC on page 6-2 • NVIC functional description on page 6-3 • NVIC programmers model on page 6-4. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Nested Vectored Interrupt Controller 6.1 About the NVIC The NVIC provides configurable interrupt handling abilities to the processor. It: • facilitates low-latency exception and interrupt handling • controls power management. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Nested Vectored Interrupt Controller 6.2 NVIC functional description The NVIC supports up to 240 interrupts each with up to 256 levels of priority. You can change the priority of an interrupt dynamically. The NVIC and the processor core interface are closely coupled, to enable low latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the stacked, or nested, interrupts to enable tail-chaining of interrupts.
Nested Vectored Interrupt Controller 6.3 NVIC programmers model Table 6-1 shows the NVIC registers.
Nested Vectored Interrupt Controller Table 6-2 shows the ICTR bit assignments. Table 6-2 ICTR bit assignments Bits Name Function [31:4] - Reserved. [3:0] INTLINESNUM Total number of interrupt lines in groups of 32: 0b0000 = 0...32 0b0001 = 33...64 0b0010 = 65...96 0b0011 = 97...128 0b0100 = 129...160 0b0101 = 161...192 0b0110 = 193...224 0b0111 = 225...256a a. The processor supports a maximum of 240 external interrupts. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited.
Chapter 7 Debug This chapter describes how to debug and test software running on the processor. It contains the following sections: • About debug on page 7-2 • About the AHB-AP on page 7-6 • About the Flash Patch and Breakpoint Unit (FPB) on page 7-9. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Debug 7.1 About debug The processor implementation determines the debug configuration, including whether debug is implemented. If the processor does not implement debug, no ROM table is present and the halt, breakpoint, and watchpoint functionality is not present. Basic debug functionality includes processor halt, single-step, processor core register access, Vector Catch, unlimited software breakpoints, and full system memory access. See the ARMv7-M Architectural Reference Manual for more information.
Debug 2. Follow the pointers in that Cortex-M3 ROM table: a. System Control Space (SCS) b. Breakpoint unit (BPU) c. Data watchpoint unit (DWT). See Table 7-2 on page 7-4 for more information. When a debugger identifies the SCS from its CoreSight identification, it can identify the processor and its revision number from the CPUID register in the SCS at address 0xE000ED00. A debugger cannot rely on the Cortex-M3 ROM table being the first ROM table encountered.
Debug Table 7-2 shows the CoreSight components that the Cortex-M3 ROM table points to. The values depend on the implemented debug configuration.
Debug SCS CoreSight identification Table 7-3 shows the SCS CoreSight identification registers and values for debugger detection. Final debugger identification of the Cortex-M3 processor is through the CPUID register in the SCS. See CPUID Base Register, CPUID on page 4-5.
Debug 7.2 About the AHB-AP The AHB-AP is a Memory Access Port (MEM-AP) as defined in the ARM Debug Interface v5 Architecture Specification. The AHB-AP is an optional debug access port into the Cortex-M3 system, and provides access to all memory and registers in the system, including processor registers through the SCS. System access is independent of the processor status. Either SW-DP or SWJ-DP is used to access the AHB-AP. The AHB-AP is a master into the Bus Matrix.
Debug Configurations This register is available in all processor configurations. Attributes See the register summary in Table 7-5 on page 7-6. Figure 7-2 shows the CSW bit assignments. 31 30 29 28 26 25 24 12 11 Mode Reserved Hprot1 Reserved MasterType Reserved 8 7 6 5 4 3 2 0 Size TransInProg DbgStatus AddrInc Reserved Figure 7-2 CSW bit assignments Table 7-6 shows the CSW bit assignments. Table 7-6 CSW bit assignments ARM DDI 0337I ID072410 Bits Name Function [31:30] - Reserved.
Debug Table 7-6 CSW bit assignments (continued) Bits Name Function [5:4] AddrInc Auto address increment and pack mode on Read or Write data access. Only increments if the current transaction completes with no error. Auto address incrementing and packed transfers are not performed on access to Banked Data registers 0x10 - 0x1C. The status of these bits is ignored in these cases. Increments and wraps within a 4-KB address boundary, for example from 0x1000 to 0x1FFC.
Debug 7.3 About the Flash Patch and Breakpoint Unit (FPB) The FPB: • implements hardware breakpoints • patches code and data from Code space to System space. A full FPB unit contains: • Two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space. • Six instruction comparators for matching against instruction fetches from Code space, and remapping to a corresponding area in System space.
Debug 7.3.2 FPB programmers model Table 7-7 shows the FPB registers. Depending on the implementation of your processor, some of these registers might not be present. Any register that is configured as not present reads as zero.
Chapter 8 Data Watchpoint and Trace Unit This chapter describes the Data Watchpoint and Trace (DWT) unit. It contains the following sections: • About the DWT on page 8-2 • DWT functional description on page 8-3 • DWT Programmers Model on page 8-4. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Data Watchpoint and Trace Unit 8.1 About the DWT The DWT is an optional debug unit that provides watchpoints, data tracing, and system profiling for the processor. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Data Watchpoint and Trace Unit 8.2 DWT functional description A full DWT contains four comparators that you can configure as • a hardware watchpoint • an ETM trigger • a PC sampler event trigger • a data address sampler event trigger. The first comparator, DWT_COMP0, can also compare against the clock cycle counter, CYCCNT. You can also use the second comparator, DWT_COMP1, as a data comparator. A reduced DWT contains one comparator that you can use as a watchpoint or as a trigger.
Data Watchpoint and Trace Unit 8.3 DWT Programmers Model Table 8-1 lists the DWT registers. Depending on the implementation of your processor, some of these registers might not be present. Any register that is configured as not present reads as zero.
Data Watchpoint and Trace Unit Table 8-1 DWT register summary (continued) Address Name Type Reset Description 0xE0001FF0 CID0 RO 0x0D Component identification registers 0xE0001FF4 CID1 RO 0xE0 0xE0001FF8 CID2 RO 0x05 0xE0001FFC CID3 RO 0xB1 a.
Chapter 9 Instrumentation Trace Macrocell Unit This chapter describes the Instrumentation Trace Macrocell (ITM) unit. It contains the following sections: • About the ITM on page 9-2 • ITM functional description on page 9-3 • ITM programmers model on page 9-4. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Instrumentation Trace Macrocell Unit 9.1 About the ITM The ITM is a an optional application-driven trace source that supports printf() style debugging to trace operating system and application events, and generates diagnostic system information. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Instrumentation Trace Macrocell Unit 9.2 ITM functional description The ITM generates trace information as packets. Multiple sources can generate packets. If multiple sources generate packets at the same time, the ITM arbitrates the order in which packets are output. These sources in decreasing order of priority are: ARM DDI 0337I ID072410 • Software trace. Software can write directly to ITM stimulus registers to generate packets. • Hardware trace.
Instrumentation Trace Macrocell Unit 9.3 ITM programmers model Table 9-1 shows the ITM registers. Depending on the implementation of your processor, the ITM registers might not be present. Any register that is configured as not present reads as zero. • • Note You must enable TRCENA of the Debug Exception and Monitor Control Register before you program or use the ITM. If the ITM stream requires synchronization packets, you must configure the synchronization packet rate in the DWT.
Instrumentation Trace Macrocell Unit 9.3.1 ITM Trace Privilege Register, ITM_TPR The ITM_TPR characteristics are: Purpose Enables an operating system to control the stimulus ports that are accessible by user code. Usage constraints You can only write to this register in privileged mode. Configurations This register is available if the ITM is configured in your implementation. Attributes See Table 9-1 on page 9-4. Figure 9-1 shows the ITM_TPR bit assignments.
Chapter 10 Embedded Trace Macrocell This chapter describes the Embedded Trace Macrocell (ETM). It contains the following sections: • About the ETM on page 10-2 • ETM functional description on page 10-3 • ETM Programmers model on page 10-9 ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Embedded Trace Macrocell 10.1 About the ETM The ETM is an optional debug component that enables reconstruction of program execution. The ETM is designed to be a high-speed, low-power debug tool that only supports instruction trace. This ensures that area is minimized, and that gate count is reduced. The ETM implements ARM ETM architecture v3.5. See the ARM Embedded Trace Macrocell Architecture Specification. The ETM traces all 32-bit Thumb instructions as a single instruction.
Embedded Trace Macrocell 10.2 ETM functional description Figure 10-1 shows a block diagram of the ETM, and shows how the ETM interfaces to the Trace Port Interface Unit (TPIU).
Embedded Trace Macrocell Table 10-1 lists the Cortex-M3 resources. Table 10-1 Cortex-M3 resources ARM DDI 0337I ID072410 Feature Present on ETM-M3 Architecture version ETMv3.
Embedded Trace Macrocell Table 10-1 Cortex-M3 resources (continued) Feature Present on ETM-M3 Load PC first No Fetch comparisons No Load data traced No Resource identification encoding You configure the trace enable event and trigger event using the same mechanism. For each event, a 17-bit register is used to define the event. This register provides: • Resource A, bits [6:0] • Resource B, bits [13:7] • a Boolean function, bits [16:14]. Table 10-2 shows the encodings used for the Boolean function.
Embedded Trace Macrocell 10.2.2 Timestamp format Timestamps are encoded as 48-bit natural binary numbers. A system implementation may provide a timestamp count which can be used by several trace sources as an aid to correlating the trace streams. 10.2.3 Periodic synchronization The ETM uses a fixed synchronization packet generation frequency of every 1024 bytes of trace. 10.2.
Embedded Trace Macrocell 10.2.7 Triggering The ETM provides a trigger resource that can be used to identify a point within a trace run. The generation of a trigger does not affect the tracing in any way, but the trigger will be output in the trace stream, and can also be passed to other trace components or used to halt the processor. An external trace port analyzer can use the trigger to determine when to start and stop capture of trace. 10.2.
Embedded Trace Macrocell Table 10-5 Trigger output connections 10.2.9 Trigger bit Destination signal Destination device Comments [7] User defined - - [6] User defined - - [5] ETMEXTIN[1] ETM Compulsory if ETM is present. [4] ETMEXTIN[0] ETM Compulsory if ETM is present. [3] INTISR[y] NVIC Recommended if an ETB is present. If multiple cores share a single ETB, you must only connect to the CTI of one of the cores. [2] INTISR[x] NVIC Compulsory. Any interrupt can be used.
Embedded Trace Macrocell 10.3 ETM Programmers model This section describes the mechanisms for programming the registers used to set up the trace and triggering facilities of the macrocell. The programmers model enables you to use the ETM registers to control the macrocell. 10.3.1 Modes of operation and execution ETM-M3 implements ETMv3.5 for tracing 16-bit and 32-bit Thumb instructions. The Embedded Trace Macrocell Architecture Specification describes the features of ETMv3.5.
Embedded Trace Macrocell Table 10-6 ETM registers (continued) Address Name Reset Type Description 0xE00411E4 ETMIDR 0x4114F253 RO ID Register, ETMIDR on page 10-17 0xE00411E8 ETMCCER 0x18541800 RO Configuration Code Extension Register, ETMCCER on page 10-18 0xE00411F0 ETMTESSEICR - RW TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR on page 10-19 0xE00411F8 ETMTSEVR - RW Timestamp Event Register.
Embedded Trace Macrocell Table 10-6 ETM registers (continued) Address Name Reset Type Description 0xE0041FD0 ETMPIDR4 0x00000004 RO 0xE0041FD4 ETMPIDR5 0x00000000 RO Peripheral Identification registers.
Embedded Trace Macrocell Table 10-7 ETMCR bit assignments Bits Name Function [31:22] - RAZ [28] Timestamp enable When set, this bit enables timestamping. An ETM reset sets this bit to 0. [21] Port size[3] This bit is implemented but has no function. An ETM reset sets this bit to 0. [20:18] - Reserved [17:16] Port mode [1:0] These bits are implemented but have no function. An ETM reset sets these bits to 0.
Embedded Trace Macrocell Table 10-7 ETMCR bit assignments (continued) Bits Name Function [6:4] Port size [2:0] The ETM-M3 has no influence over the external pins used for trace. These bits are implemented but not used. On an ETM reset these bits reset to 0b001. [3:1] - Reserved [0] ETM power down This bit can be used by an implementation to control if the ETM is in a low power state. This bit must be cleared by the trace software tools at the beginning of a debug session.
Embedded Trace Macrocell 10.3.4 Configuration Code Register, ETMCCR The ETM Configuration Code Register characteristics are: Purpose Enables software to read the implementation-specific configuration of the ETM. Usage constraints There are no usage constraints. Configurations This register is only available if the processor is configured to use the ETM. Attributes See the ETM register summary in Table 10-6 on page 10-9. Figure 10-3 shows the ETMCCR bit assignments.
Embedded Trace Macrocell Table 10-8 ETMCCR bit assignments (continued) Bits Name Function [15:13] Number of counters The value of these bits is 0b001, indicating that one counter is implemented. [12:8] Number of memory map decoders The value of these bits is 0b00000, indicating that memory map decoder inputs are not implemented. [7:4] Number of data value comparators The value of these bits is 0b0000, indicating that data value comparators are not implemented.
Embedded Trace Macrocell Table 10-9 ETMSCR bit assignments (continued) Bits Name Function [10] Port size supported This bit reads as 1 if the currently selected port size is supported. This has no effect on the TPIU trace port. [9] Maximum port size [3] Maximum ETM port size bit [3]. This bit is used in conjunction with bits [2:0]. Its value is 0. This has no effect on the TPIU trace port. [8] FIFOFULL supported The value of this bit is 1, indicating that FIFOFULL is supported.
Embedded Trace Macrocell 10.3.7 ID Register, ETMIDR The ETMIDR characteristics are: Purpose Holds the ETM architecture variant, and defines the programmers model for the ETM. Usage constraints There are no usage constraints. Configurations This register is only available if the processor is configured to use the ETM. Attributes See the register summary in Table 10-6 on page 10-9. Figure 10-6 shows the ETMIDR bit assignments.
Embedded Trace Macrocell 10.3.8 Configuration Code Extension Register, ETMCCER The ETMCCER characteristics are: Purpose Holds ETM configuration information additional to that in the ETMCCR. See Configuration Code Register, ETMCCR on page 10-14. Usage constraints There are no usage constraints. Configurations This register is only available if the processor is configured to use the ETM. Attributes See the register summary in Table 10-6 on page 10-9. Figure 10-7 shows the ETMCCER bit assignments.
Embedded Trace Macrocell Table 10-12 ETMCCER bit assignments (continued) Bits Name Function [12] Data address comparisons The value of this bit is 1, indicating that data address comparisons are not supported. [11] Readable registers The value of this bit is 1, indicating that all registers are readable. [10:3] Extended external input bus The value of these bits is 0, indicating that the extended external input bus is not implemented.
Embedded Trace Macrocell Usage constraints There are no usage constraints. Configurations This register is only available if the processor is configured to use an ETM. Attributes See the register summary in Table 10-6 on page 10-9. Figure 10-9 shows the ETMPDSR bit assignments. 31 1 0 Reserved, RAZ ETM powered up Figure 10-9 ETMPDSR bit assignments Table 10-14 shows the ETMPDSR bit assignments. Table 10-14 ETMPDSR bit assignments Bits Name Function [31:1] - Reserved, Read-As-Zero.
Embedded Trace Macrocell Table 10-15 shows the ITMISCIN bit assignments. Table 10-15 ITMISCIN bit assignments Bits Name Function [31:5] - Reserved. [4] COREHALT A read of this bit returns the value of the COREHALT input pin. [3:2] - Reserved. [1:0] EXTIN[1:0] A read of these bits returns the value of the EXTIN[1:0] input pins. 10.3.12 Integration Test Trigger Out, ITTRIGOUT The ITMISCIN characteristics are: Purpose Integration test.
Embedded Trace Macrocell 31 1 0 Reserved ATREADY input value Figure 10-12 ETM_ITATBCTR2 bit assignments Table 10-17 shows the ETM_ITATBCTR2 bit assignments. Table 10-17 ETM_ITATBCTR2 bit assignments Bits Name Function [31:1] - Reserved [0] ATREADY input value A read of this bit returns the value of the ETM ATREADY input. 10.3.14 ETM Integration Test ATB Control 0, ETM_ITATBCTR0 The Integration Test ATB Control (ETM_ITATBCTR0) characteristics are: Purpose Integration test.
Chapter 11 Trace Port Interface Unit This chapter describes the Cortex-M3 TPIU, the Trace Port Interface Unit specific to the Cortex-M3 processor. It contains the following sections: • About the Cortex-M3 TPIU on page 11-2 • TPIU functional description on page 11-3 • TPIU programmers model on page 11-5. ARM DDI 0337I ID072410 Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.
Trace Port Interface Unit 11.1 About the Cortex-M3 TPIU The Cortex-M3 TPIU is an optional component that acts as a bridge between the on-chip trace data from the Embedded Trace Macrocell (ETM) and the Instrumentation Trace Macrocell (ITM), with separate IDs, to a data stream. The TPIU encapsulates IDs where required, and the data stream is then captured by a Trace Port Analyzer (TPA). The Cortex-M3 TPIU is specially designed for low-cost debug. It is a special version of the CoreSight TPIU.
Trace Port Interface Unit 11.2 TPIU functional description There are two configurations of the TPIU: • A configuration that supports ITM debug trace. • A configuration that supports both ITM and ETM debug trace. If your implementation requires no trace support then the TPIU might not be present. Note If your Cortex-M3 system uses the optional ETM component, the TPIU configuration supports both ITM and ETM debug trace. See Chapter 10 Embedded Trace Macrocell. 11.2.
Trace Port Interface Unit 11.2.3 Serial Wire Output format The TPIU can output trace data in a Serial Wire Output (SWO) format: • TPIU_DEVID specifies the formats that are supported. See TPIU_DEVID on page 11-12. • TPIU_SPPR specifies the SWO format in use. See the ARMv7-M Architecture Reference Manual. When one of the two SWO modes is selected, you can enable the TPIU to bypass the formatter for trace output. If the formatter is bypassed, only the ITM and DWT trace source passes through.
Trace Port Interface Unit 11.3 TPIU programmers model Table 11-1 provides a summary of the TPIU registers. Depending on the implementation of your processor, the TPIU registers might not be present, or the CoreSight TPIU might be present instead. Any register that is configured as not present reads as zero.
Trace Port Interface Unit The following sections describe the TPIU registers whose implementation is specific to this processor. The Formatter, Integration Mode Control, and Claim Tag registers are described in the CoreSight Components Technical Reference Manual. Other registers are described in the ARMv7-M Architecture Reference Manual. 11.3.1 Asynchronous Clock Prescaler Register, TPIU_ACPR The TPIU_ACPR characteristics are: Purpose Scales the baud rate of the asynchronous output.
Trace Port Interface Unit Table 11-3 shows the TPIU_FFSR bit assignments. Table 11-3 TPIU_FFSR bit assignments 11.3.3 Bits Name Function [31:4] - Reserved [3] FtNonStop Formatter cannot be stopped [2] TCPresent This bit always reads zero [1] FtStopped This bit always reads zero [0] FlInProg This bit always reads zero Formatter and Flush Control Register, TPIU_FFCR The TPIU_FFCR characteristics are: Purpose Controls the TPIU formatter. Usage constraints There are no usage constraints.
Trace Port Interface Unit When one of the two SWO modes is selected, bit [1] of TPIU_FFCR enables the formatter to be bypassed. If the formatter is bypassed, only the ITM and DWT trace source passes through. The TPIU accepts and discards data from the ETM. This function is can be used to connect a device containing an ETM to a trace capture device that is only able to capture SWO data. Enabling or disabling the formatter causes momentary data corruption.
Trace Port Interface Unit 31 30 29 28 27 26 25 24 23 16 15 0 8 7 ETM data 2 ETM data 1 ETM data 0 ETM byte count ETM ATVALID ITM byte count ITM ATVALID Reserved Figure 11-6 Integration ETM Data bit assignments Table 11-6 shows the Integration ETM Data bit assignments. Table 11-6 Integration ETM bit assignments Bits Name Function [31:30] - Reserved [29] ITM ATVALID input Returns the value of the ITM ATVALID signal.
Trace Port Interface Unit Table 11-7 shows the ITATBCTR2 bit assignments. Table 11-7 ITATBCTR2 bit assignments 11.3.7 Bits Name Function [31:1] - Reserved [0] ATREADY1, ATREADY2 This bit sets the value of both the ETM and ITM ATREADY outputs, if the TPIU is in integration test mode. Integration ITM Data The Integration ITM Data characteristics are: Purpose Trace data integration testing. Usage constraints You must set bit [1] of TPIU_ITCTRL to use this register.
Trace Port Interface Unit 11.3.8 ITATBCTR0 The ITATBCTR0 characteristics are: Purpose Integration test. Usage constraints There are no usage constraints. Configurations This register is available in all processor configurations. Attributes See Table 11-1 on page 11-5. Figure 11-9 shows the ITATBCTR0 bit assignments. 1 0 31 Reserved ATVALID1 ATVALID2 Figure 11-9 ITATBCTR0 bit assignments Table 11-9 shows the ITATBCTR0 bit assignments. Table 11-9 ITATBCTR0 bit assignments 11.3.
Trace Port Interface Unit Table 11-10 shows the TPIU_ITCTRL bit assignments. Table 11-10 TPIU_ITCTRL bit assignments Bits Name Function [31:2] - Reserved. [1:0] Mode Specifies the current mode for the TPIU: 0b00 normal mode 0b01 integration test mode 0b10 integration data test mode 0b11 Reserved. In integration data test mode, the trace output is disabled, and data can be read directly from each input port using the integration data registers. 11.3.
Trace Port Interface Unit Table 11-11 TPIU_DEVID bit assignments (continued) Bits Name Function [8:6] Minimum buffer size Specifies the minimum TPIU buffer size: 0b010 = 4 bytes. [5] Asynchronous TRACECLKIN [4:0] Number of trace inputs Specifies whether TRACECLKIN can be asynchronous to CLK: 0b1 = TRACECLKIN can be asynchronous to CLK. Specifies the number of trace inputs: 0b000000 = 1 input 0b000001 = 2 inputs If your implementation includes an ETM, the value of this field is 0b00001. 11.3.
Appendix A Revisions This appendix describes the technical changes between released issues of this book. Table A-1 Differences between issue E and issue F Change Location Introductory processor information updated Issue H distributes this information between About the processor on page 1-2 and Features on page 1-3 and removes duplicate information from these sections.
Revisions Table A-1 Differences between issue E and issue F (continued) Change Location Definition of ICI field of Execution Program Status Register updated Issue H removes this information. Table of nonsupported Thumb instructions removed. Second footnote on Table 5-1 removed. Issue H removes this information. Addition of note to vector table and reset description Description of SLEEPING and SLEEPDEEP signals updated.
Revisions Table A-1 Differences between issue E and issue F (continued) Change Location HCLK and CLK replaced by FCLK Issue H removes this information.
Revisions Table A-2 Differences between issue F and issue G Change Location Wake-up Interrupt Controller (WIC) added to Cortex-M3 block diagram Figure 2-1 on page 2-2 Section 1-2 and section 1-3 combined Issue H distributes this information between Features on page 1-3, Interfaces on page 1-4, and Configurable options on page 1-5.
Revisions Table A-2 Differences between issue F and issue G (continued) Change Location Change to timing information for ETMIVALID Issue H removes this information.
Revisions Table A-3 Differences between issue G and issue H (continued) Change Location Descriptions of the memory system and of exceptions moved to Chapter 3. Chapter 3 Programmers Model Component-specific registers moved from System Control chapter to appropriate chapters within the manual. Chapter 4 System Control Deleted Clocking and Resets chapter. See the implementation documentation for the processor. Deleted Power Management chapter.
Revisions Table A-4 Differences between issue H and issue I (continued) Change Location Added Timestamp format information. Timestamp format on page 10-6 Added ETM register descriptions. Table 10-6 on page 10-9 Added ETMCNTRLDVR1 ETM register. Table 10-6 on page 10-9 Changed reset values for ETMVCCR and ETMCCER. Table 10-6 on page 10-9 Updated ETMCR register bit assignments. Table 10-7 on page 10-12 Updated ETMCCR bit assignments. Table 10-8 on page 10-14 Updated ETMCCER bit assignments.
Glossary This glossary describes some of the terms used in technical documents from ARM. Abort A mechanism that indicates to a core that the attempted memory access is invalid or not allowed or that the data returned by the memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid or protected instruction or data memory. See also Data Abort, External Abort and Prefetch Abort.
Glossary Advanced Peripheral Bus (APB) A simpler bus protocol than AXI and AHB. It is designed for use with ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. Connection to the main system bus is through a system-to-peripheral bus bridge that helps to reduce system power consumption. AHB See Advanced High-performance Bus. AHB Access Port (AHB-AP) An optional component of the DAP that provides an AHB interface to a SoC. AHB-AP See AHB Access Port.
Glossary Base register A register specified by a load or store instruction that is used to hold the base value for the address calculation for the instruction. Depending on the instruction and its addressing mode, an offset can be added to or subtracted from the base register value to form the address that is sent to memory.
Glossary Byte An 8-bit data item. Byte-invariant In a byte-invariant system, the address of each byte of memory remains unchanged when switching between little-endian and big-endian operation. When a data item larger than a byte is loaded from or stored to memory, the bytes making up that data item are arranged into the correct order depending on the endianness of the memory access. The ARM architecture supports byte-invariant systems in ARMv6 and later versions.
Glossary Embedded Trace Macrocell (ETM) A hardware macrocell that, when connected to a processor core, outputs instruction trace information on a trace port. Endianness The scheme that determines the order of successive bytes of a data word when it is stored in memory. See also Little-endian and Big-endian ETB See Embedded Trace Buffer. ETM See Embedded Trace Macrocell.
Glossary Instruction cycle count The number of cycles for which an instruction occupies the Execute stage of the pipeline. Instrumentation trace A component for debugging real-time systems through a simple memory-mapped trace interface, providing printf() style debugging. Intelligent Energy Management (IEM) A technology that enables dynamic voltage scaling and clock frequency variation to be used to reduce power consumption in a device. Internal PPB PPB memory space at 0xE0000000 to 0xE003FFFF.
Glossary Memory coherency A memory is coherent if the value read by a data read or instruction fetch is the value that was most recently written to that location. Memory coherency is made difficult when there are multiple possible physical locations that are involved, such as a system that has main memory, a write buffer and a cache. Memory Protection Unit (MPU) Hardware that controls access permissions to blocks of memory. Unlike an MMU, an MPU does not modify addresses. Microprocessor See Processor.
Glossary Prefetch Abort An indication from a memory system to the core that an instruction has been fetched from an illegal memory location. An exception must be taken if the processor attempts to execute the instruction. A Prefetch Abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction memory. See also Data Abort, Abort. Prefetch Unit (PFU) The PFU fetches instructions from the memory system that can supply one word each cycle.
Glossary Thread Control Block A data structure used by an operating system kernel to maintain information specific to a single thread of execution. Thumb instruction A halfword that specifies an operation for an ARM processor in Thumb state to perform. Thumb instructions must be halfword-aligned. Thumb state A processor that is executing Thumb (16-bit) halfword aligned instructions is operating in Thumb state. TPA See Trace Port Analyzer. TPIU See Trace Port Interface Unit.
