Specifications

Cortex-M3 / Cortex-M3 with ETM (AT420/AT425)

Date of Issue: 12-Nov-2008 ARM Errata Notice Document Revision 2.0

PR326-PRDC-009450 v2.0

Non Confidential

602117: LDRD with base in list may result in incorrect base register when interrupted

or faulted

Status

Affects: product Cortex-M3, Cortex-M3 with ETM.

Fault status: Cat 2, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0,r2p0-00rel0, Open.

Description

LDRD with the base register in the list of the form LDRD Ra, Rb, [Ra, #imm] may not complete after the

load of the first destination register due to an interrupt before the completion of the second load or due to the

second load getting a bus fault or an MPU fault. Since the base register has been updated the base register

must be restored to its original value before entering the appropriate interrupt or fault handler so that the

instruction can restart correctly upon return from the handler. In certain circumstances this may not occur as

required.

When the LDRD is interrupted in between the two loads then the base register may not be restored as required.

This can only happen when the instructions are being executed from the system bus (address 0x20000000 and

above) and the loaded data is also being read from the system bus.

For the fault case where the second load gets a bus fault or an MPU fault then the base register is never

restored and there is no dependence on which bus the instructions are being executed from.

When the base register is the second register in the LDRD list, of the form LDRD Rb, Ra, [Ra, #imm], then

this erratum cannot occur.

You will not be affected by this erratum if:

1. you do not execute code from the system bus and if your code bus does not generate bus faults and

you do not execute LDRD’s that cross MPU boundaries, or

2. if your compiler does not generate LDRD’s

Conditions

Either:

1. An LDRD is being executed where the base register is in the list and write-back is not used:

LDRD Ra, Rb, [Ra, #imm]

2. Instructions and data are both being fetched via the system bus. This occurs for locations in memory

greater than 0x20000000.

3. The first LDRD address is prioritised and issued to the system bus, whilst the instruction fetch is

internally waited. The instruction fetch is issued to the system bus upon completion of the first part of

the LDRD. The second part of the LDRD is issued to the system bus upon completion of the instruction

fetch.

4. An interrupt occurs in between the two load operations.

Or:

1. An LDRD is being executed where the base register is in the list and write-back is not used:

LDRD Ra, Rb, [Ra, #imm]

2. A bus fault or MPU fault occurs for the second load.