Specifications

Cortex-M3 / Cortex-M3 with ETM (AT420/AT425)

Date of Issue: 12-Nov-2008 ARM Errata Notice Document Revision 2.0

PR326-PRDC-009450 v2.0

Non Confidential

463764: Core may freeze for SLEEPONEXIT single instruction ISR

Status

Affects: product Cortex-M3, Cortex-M3 with ETM.

Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0.

Description

The SLEEPONEXIT functionality causes the core to enter the sleep mode when the exit from the sole active

interrupt occurs. This means that there are no more interrupts active and the exit would have caused a return to

the thread.

It is possible for the core to become frozen if the SLEEPONEXIT functionality is used and the interrupt service

routine (ISR) concerned only contains a single instruction. This freezing may occur if only one interrupt is active

and it is pre-empted by an interrupt whose handler only contains the single instruction. This instruction must be

a legal ISR exit instruction that takes one cycle to execute (either a BX or a BLX). In this case the unstacking

would occur after the single instruction had been executed as normal to return to the now only active interrupt

handler. However, once it has returned no more instructions will be processed and the core will be frozen. Any

new pre-empting interrupt will unfreeze the processor.

Conditions

1. SLEEPONEXIT (bit 1) in the System Control Register at address 0xE000ED10 is set.

2. An interrupt occurs that causes a pre-emption of the current ISR which is the only interrupt that is

currently active.

3. The interrupt service routine that is entered consists of only one instruction (either BX or BLX) which

causes a legal exit from that ISR.

Implications

The core may freeze and stop processing instructions when it returns to the only currently active ISR. Note that

a new interrupt that causes a pre-emption would cause the core to become unfrozen and behave correctly

again.

Workaround

If the SLEEPONEXIT functionality is required then do not allow an ISR to contain only one instruction. If an

empty ISR is used then insert a NOP before the exit instruction.