Specifications

Cortex-M3 / Cortex-M3 with ETM (AT420/AT425)
Date of Issue: 12-Nov-2008 ARM Errata Notice Document Revision 2.0
PR326-PRDC-009450 v2.0
© Copyright ARM Limited 2008. All rights reserved. Page 16 of 20
Non Confidential
463763: BKPT in debug monitor mode can cause DFSR mismatch
Status
Affects: product Cortex-M3, Cortex-M3 with ETM.
Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0.
Description
A BKPT may be executed in debug monitor mode which will cause the debug monitor handler to be run but the
Debug Fault Status Register (DFSR) at address 0xE000ED30 will not have bit 1 set to indicate the cause was a
BKPT instruction. This will only occur if an interrupt other than the Debug Monitor is already being processed
just before the BKPT is executed.
Conditions
1. C_DEBUGEN (bit 0) in the Debug Halting Control and Status Register at address 0xE000EDF0 is 0.
2. MON_EN (bit 16) in the Debug Exception and Monitor Control Register at address 0xE000EDFC is 1.
3. An enabled interrupt occurs two cycles before the BKPT is executed that causes a pre-emption.
Implications
The Debug Monitor handler may be entered without the DFSR revealing the cause of the handler being entered.
Workaround
Should a workaround be required, it can be deduced that if the DFSR does not have any bits set when the
debug monitor has been entered then the cause must be due to this corner case and that it was the result of a
BKPT.