Specifications

Cortex-M3 / Cortex-M3 with ETM (AT420/AT425)
Date of Issue: 12-Nov-2008 ARM Errata Notice Document Revision 2.0
PR326-PRDC-009450 v2.0
© Copyright ARM Limited 2008. All rights reserved. Page 14 of 20
Non Confidential
538714: Cortex-M3 TPIU Clock Domain crossing
Status
Affects: product Cortex-M3, Cortex-M3 with ETM.
Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0.
Description
Combinatorial paths exist in control signals crossing the asynchronous clock boundary between FCLK and
TRACECLKIN.
Some of these signals control the reading and writing of data in the trace data FIFO on both sides of the FCLK
and TRACECLKIN clock boundary and therefore could cause old data to be repeated or new data to be lost.
Conditions
1. FCLK/HCLK is asynchronous to TRACECLKIN
Implications
When FCLK and TRACECLKIN are asynchronous and depending on the silicon implementation of the block,
trace data might become corrupted.
Workaround
This is a workaround for system implementers. System implementers should make FCLK and TRACECLKIN
operate synchronously. To avoid the possibility of corrupted trace data, the Trace Port must be fed with a clock
synchronous to FCLK. Any crossing to an asynchronous TRACECLKIN domain should be done externally
before the TPIU via a separate ATB asynchronous bridge.