User guide

RealView Logic Tile
ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved. F-13
Figure F-6 Bus signals for RealView Logic Tile and FPGA
S Master
M1
Slaves
M2 Default Slave
ARM926EJ-S
Dev. Chip
FPGA
Slave
Master
Arbiter
AHB S
AHB M1
AHB M2
PCI control
PCI connector
HGRANTM2
Master
Decoder
Logic Tile
HLOCKM2
HGRANTM1
HLOCKM1
HREADYM2
HRESPM2
1
1
1
HREADYS
0
S
Decoder
HMASTLOCK
HRESPS
HSELS
LTHGRANT
LTBUSREQ
GRANT
BUSREQ
HADDRx
nTILEDET
HREADYM1
001010
11
0
S S S
HRESPM1
M
PCI
interface
S
S
S
M2
Decoder
1
Slave
Master
Master
Slave
1
10
N/C
N/C