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Programmer’s Reference
ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved. 4-93
Table 4-68 Register values for Samsung SRAM
Address
Name of SSMC
register
Value Description
+0x40 SMBIDCYR2
0x0 Idle Cycle Control Register for bank 2
+0x44 SMBWSTRDR2
0x2 Read Wait State Control Reg bank 2
+0x48 SMBWSTWRR2
0x2 Write Wait State Control Reg Bank 2
+0x4c SMBWSTOENR2
0x0 Output Enable Assertion Delay 2
+0x50 SMBWSTWENR2
0x1 Write Enable Assertion Delay 2
+0x54 SMBCR2
0x303021 Control Register for memory bank 2
+0x5c SMBWSTBRDR2
0x0 Burst Read Wait state Control Reg 2
Table 4-69 Register values for Spansion BDS640
Address
Name of SSMC
register
Value Description
+0x60 SMBIDCYR3
0x0 Idle Cycle Control Register for bank 3
+0x64 SMBWSTRDR3
0x3 Read Wait State Control Reg bank 3
+0x68 SMBWSTWRR3
0x2 Write Wait State Control Reg Bank 3
+0x6c SMBWSTOENR3
0x0 Output Enable Assertion Delay 3
+0x70 SMBWSTWENR3
0x1 Write Enable Assertion Delay 3
+0x74 SMBCR3
0x303021 Control Register for memory bank 3
+0x7c SMBWSTBRDR3
0x0 Burst Read Wait state Control Reg 3
Table 4-70 Register values for Spansion LV256
Address
Name of SSMC
register
Value Description
+0x80 SMBIDCYR4
0x0 Idle Cycle Control Register for bank 4
+0x84 SMBWSTRDR4
0x4 Read Wait State Control Reg bank 4
+0x88 SMBWSTWRR4
0x3 Write Wait State Control Reg Bank 4