User guide

Programmer’s Reference
ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved. 4-75
The PCI slave bridge connected to AHB M2 recognizes addresses 0x41000000 to
0x6FFFFFFF as being intended for a target within the PCI address space of the memory
map, and passes accesses within this region to the PCI bus. The PCI master bridge
connected to the PCI bus passes accesses to the AHB S bus.
There are windows that provide access from the AHB M2 bus to the PCI expansion bus
are listed in Table 4-49.
4.17.1 Control registers
The SYS_PCICTL, PCI_SELFID, and PCI_FLAGS control the operation of the PCI
bus and provide status information. The PCI_IMAPx and PCI_SMAPx registers define
the address translation values for the PCI I/O, PCI configuration, and PCI memory
windows. See Table 4-50. The default value for all mapping registers is
0x0 .
Table 4-49 PCI bus memory map for AHB M2 bridge
Usage Size AHB M2 address
PCI self config 16MB
0x41000000–0x41FFFFFF
PCI config 16MB 0x42000000–0x42FFFFFF
PCI I/O 16MB 0x43000000–0x43FFFFFF
PCI memory region 0 256MB 0x44000000–0x4FFFFFFF
PCI memory region 1 256MB 0x50000000–0x5FFFFFFF
PCI memory region 2 256MB 0x60000000–0x6FFFFFFF
Table 4-50 PCI controller registers
Address Name Access Description
0x10000044 SYS_PCICTL R/W Read returns a HIGH in bit 0 if a PCI board is present in the expansion
backplane.
0x10001000 PCI_IMAP0 R/W Translate AHB M2 address to PCI address for accesses
0x44000000–0x4FFFFFFF .
0x10001004 PCI_IMAP1 R/W Translate AHB address to PCI address for accesses
0x50000000–0x5FFFFFFF .
0x10001008 PCI_IMAP2 R/W Translate AHB address to PCI address for accesses
0x60000000–0x6FFFFFFF .
0x1000100C PCI_SELFID R/W Slot location of the PB926EJ-S.