User guide

Programmer’s Reference
ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved. 4-37
4.3.18 DMA peripheral map registers, SYS_DMAPSRx
The DMA map registers, SYS_DMAPSR0 to SYS_DMAPSR3, permit the mapping of
DMA channels 0, 1, and 2 to three of the external peripherals.
The registers are set to zero by a reset. The DMA mapping is disabled by default.
Table 4-19 on page 4-38 lists the bit assignments. See Direct Memory Access Controller
and mapping registers on page 4-52 for more information on the DMA logic.
Figure 4-18 DMA mapping register
[2] Read/write FPGA remap control (FPGA_REMAP)
[1] Read RTCOUT signal from the external DS1338 real-time
clock. This 32kHz signal can be used as a timer.
[0] Read nTILEDET signal. Pulled LOW if a RealView Logic Tile
is connected to the expansion headers.
Table 4-17 SYS_MISC (continued)
Bits Access Description
Table 4-18 DMA map registers
Name Address Access Description
SYS_DMAPSR0
0x10000064 Read/write controls mapping of external
peripheral DMA request and
acknowledge signals to DMA channel
0
SYS_DMAPSR1 0x10000068 Read/write controls mapping to DMA channel 1
SYS_DMAPSR2
0x1000006C Read/write controls mapping to DMA channel 2