User guide

Programmer’s Reference
4-36 Copyright © 2003-2010 ARM Limited. All rights reserved. ARM DUI 0224I
4.3.16 24MHz Counter, SYS_24MHZ
The SYS_24MHZ register at
0x1000005C provides a 32-bit count value. The count
increments at 24MHz frequency from the 24MHz crystal reference output
REFCLK24MHZ from OSC0. The register is set to zero by a reset.
4.3.17 Miscellaneous System Control Register, SYS_MISC
The SYS_MISC register at
0x10000060 provides miscellaneous status and control
signals as shown in Table 4-17.
Figure 4-17 SYS_MISC
Table 4-17 SYS_MISC
Bits Access Description
[31:13] - Reserved. Use read-modify-write to preserve value.
[12] Read/write Set HIGH to permit either a LOW on LogicTile signal
XL[136] or a PCI core interrupt to drive PCI P_nINTA
LOW.
Set LOW to permit only a PCI core interrupt to drive PCI
P_nINTA LOW.
[11:8] Read Reserved. (ETMEXTOUT[3:0] state is used to detect if
the development chip is an emulation).
[7:5] - Reserved. Use read-modify-write to preserve value.
[4] Read GP PUSHSWITCH state. If pressed, the value is 1. (See
User switches and LEDs on page 3-87.)
[3] Read/write Suspend Enable. Set HIGH to allow the GP
PUSHSWITCH to toggle the PWRFAIL pin on
ARM926EJ-S PXP Development Chip. The PWRFAIL
pin is not connected to any power-fail logic, but the pin can
be used to test application code that must respond to a
power failure.
Reserved
531 0124
TILEDET
781113
RTCOUT
FPGA
SUS EN
GP Push
3
ETMEXTOUT
Reserved
P_nINTA
12