User guide

Hardware Description
ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved. 3-89
Figure 3-38 UARTs block diagram
The signals from the ARM926EJ-S PXP Development Chip are converted from logic
level to RS232 level by MAX3243E buffers as shown in Figure 3-39 and Figure 3-40
on page 3-90.
Figure 3-39 UART0 interface
J10AJ10BJ11AJ11B
Versatile
Logic Tile
RS232 RS232 RS232 RS232
ARM926EJ-S Dev. Chip
PL011
PrimeCell
PL011
PrimeCell
PL011
PrimeCell
PL011
PrimeCell
FPGA
SER0x
UART3x output signals
UART2x input signals
UART2x output signals
UART1x input signals
UART1x output signals
UART0x input signals
UART0x output signals
SER0x
SER1x
SER1x
SER2x
SER2x
SER3x
SER3xUART3x input signals
nDRVINEN1
nDRVINEN0
AHBM2
UART0 IrDA signals