Specifications

Memory Map and Memory Configuration
3-22 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
Figure 3-10 shows the normal decoding.
Figure 3-10 Default AHB memory map with no bridge remap and SMC
0x00000000
SMC configuration
registers
MPMC configuration
registers
CLCD
DMAC
VIC
AHB Monitor
Core APB
DMA APB
MBX
AHB Bridge 1 to Off-
chip Peripherals
0x0FFFFFFF
0x80000000
0xFFFFFFFF
0x70000000
0x7FFFFFFF
0x41000000
0x6FFFFFFF
0x40000000
0x40FFFFFF
0x20000000
0x2FFFFFFF
0x10200000
0x1FFFFFFF
0x30000000
0x3FFFFFFF
0x101F0000
0x101FFFFF
0x101E0000
0x101EFFFF
0x101D0000
0x101DFFFF
0x10150000
0x101CFFFF
0x10140000
0x1014FFFF
0x10130000
0x1013FFFF
0x10120000
0x1012FFFF
0x10110000
0x1011FFFF
0x10100000
0x1010FFFF
0x10000000
0x100FFFFF
ARM D
AHB Bridge 2 to Off-
chip Peripherals
Expansion AHB S ARM I, LCD & DMA1DMA0
AHB Bridge 2 to Off-
chip Peripherals
AHB Monitor
Core APB
DMA APB DMA APB
SSMC SSMC SSMC
SSMC SSMC SSMC
AHB Bridge 1 to Off-
chip Peripherals
AHB Bridge 1 to Off-
chip Peripherals
AHB Bridge 1 to Off-
chip Peripherals
AHB Bridge 2 to Off-
chip Peripherals
AHB Bridge 2 to Off-
chip Peripherals
AHB Bridge 2 to Off-
chip Peripherals
nSTATICCS3
nSTATICCS2
nSTATICCS1
nSTATICCS0
nSTATICCS7
nSTATICCS6
nSTATICCS5
nSTATICCS4
AHB Bridge 2 to Off-
chip Peripherals
AHB Bridge 2 to Off-
chip Peripherals
AHB Bridge 2 to Off-
chip Peripherals
AHB Bridge 2 to Off-
chip Peripherals
AHB Bridge 2 to Off-
chip Peripherals
nSTATICCS3
nSTATICCS2
nSTATICCS1
nSTATICCS0
nSTATICCS7
nSTATICCS6
nSTATICCS5
nSTATICCS4
nSTATICCS7
nSTATICCS6
nSTATICCS5
nSTATICCS4
nSTATICCS3
nSTATICCS2
nSTATICCS1
nSTATICCS0
MPMC
SDRAM
MPMCDYCS3
MPMCDYCS2
MPMC
SDRAM
MPMCDYCS3
MPMCDYCS2
MPMC
SDRAM
MPMCDYCS3
MPMCDYCS2
MPMC
SDRAM
MPMCDYCS1
MPMCDYCS0
MPMC
SDRAM
MPMCDYCS1
MPMCDYCS0
MPMC
SDRAM
MPMCDYCS1
MPMCDYCS0
AHB Bridge 2 to Off-
chip Peripherals