Specifications

Memory Map and Memory Configuration
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-21
If CFGBRIDGEMEMMAP is LOW, however, the address decoding for the AHB M1
and AHB M2 buses changes as shown in Figure 3-9. The ARM D master always
accesses the AHB M1 bus for regions not decoded by a peripheral in the ARM926EJ-S
Development Chip and all other buses access ARM M2 for regions not decoded by a
peripheral in the ARM926EJ-S Development Chip.
Figure 3-9 AHB M1 access determined by ARM D
Caution
If CFGBRIDGEMEMMAP is LOW, the ARM D and ARM I buses access different
bridges for memory accesses below
0x80000000 . This affects boot memory aliasing (see
AHB memory alias for low memory on page 3-25). You must modify applications to
reflect the different memory decoding.