Specifications

Memory Map and Memory Configuration
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-17
3.2.1 TCM
The ARM926EJ-S Development Chip contains 32KB of data Tightly Coupled Memory
(TCM) and 32KB of instruction TCM.
Note
Both TCMs operate with one wait state. The TCMs do not support DMA.
The caches, TCMs, Memory Management Unit (MMU), and most other system options
are controlled using CP15 registers. You can only access CP15 registers with
MRC and
MCR instructions in a privileged mode. CDP , LDC , STC , MCRR , and MRRC instructions, and
unprivileged
MRC or MCR instructions to CP15 cause the UNDEFINED instruction
exception to be taken.
3.2.2 Memory map for internal buses
This section shows the memory map for each of the buses in the bus matrix and for
different bus mapping configurations.
3.2.3 Selection between MPMC and SSMC as static memory controller
The chip selects for static memory are determined by the state of the MPMCnSMC
signal:
• If HIGH, the MPMC controls the static memory buses.
• If LOW, the SSMC controls static memory.
Note
Dynamic memory is always controlled by the MPMC and the MPMCnSMC signal has
no effect on the MPMC SDRAM bank select signals.
The multiplexing of the chip select signals from the MPMC and SSMC is done inside
the ARM926EJ-S Development Chip before the memory remapping circuitry modifies
the chip select lines.
This section describes the memory map after booting has completed and memory is
mapped to its normal location. For details on aliasing of memory to the boot memory
range at
0x00000000 – 0x03FFFFFF , see AHB memory alias for low memory on page 3-25.
The memory map for control signals CFGBRIDGEMEMMAP HIGH and
MPMCnSMC LOW is shown in Figure 3-6 on page 3-18.