Specifications

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. ix
List of Tables
ARM926EJ-S Development Chip Reference
Manual
Change history .............................................................................................................. ii
Table 1-1 MPMC port allocation .............................................................................................. 1-10
Table 2-1 System mode control signal states ........................................................................... 2-9
Table 2-1 External peripheral clocks and clock control signals ............................................... 2-18
Table 2-2 Configuration signal sources ................................................................................... 2-19
Table 2-3 Configuration signal destinations ............................................................................ 2-20
Table 2-4 ARM926EJ-S signals .............................................................................................. 2-30
Table 2-5 ETM signals ............................................................................................................ 2-30
Table 2-6 Reset and configuration signals .............................................................................. 2-31
Table 2-7 Clock signals ........................................................................................................... 2-32
Table 2-8 JTAG TAP signals ................................................................................................... 2-33
Table 3-1 On-chip bridge selection ......................................................................................... 3-10
Table 3-1 DMA APB peripheral base addresses ..................................................................... 3-30
Table 3-2 Core APB peripheral base addresses ..................................................................... 3-30
Table 3-1 AHB M1 signals ....................................................................................................... 3-32
Table 3-2 AHB M2 signals ....................................................................................................... 3-33
Table 3-3 AHB S signals ......................................................................................................... 3-34
Table 4-1 Cycle states ............................................................................................................... 4-4
Table 4-2 Sample output ........................................................................................................... 4-5
Table 4-3 Bus state bit patterns ................................................................................................ 4-6
Table 4-4 Bit patterns for GXI states for read channel .............................................................. 4-9