Specifications

Memory Map and Memory Configuration
3-14 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
3.1.5 Endianness
The ARM926EJ-S Development Chip supports both little-endian and big-endian
operation. The endianness required is configured using bit 7 of Register 1 of CP15 in
the ARM926EJ-S system control coprocessor. The ARM926EJ-S Development Chip
provides the BIGENDOUT output signal so that components outside the ARM926EJ-S
Development Chip can also be configured for endianness using this control.
Following a reset, the ARM926EJ-S Development Chip defaults to the endianness
defined by the CFGCPUBIGENDIN input signal (this signal connects to the internal
BIGENDINIT signal). The B-bit in the ARM926EJ-S CP15 r1 Register is set to the
same state as BIGENDINIT at the time of reset. When BIGENDINIT=0 then
little-endian mode is selected.