Specifications

Memory Map and Memory Configuration

The multiplexor control determines which of the bridge clocking modes is to be used as

shown in Table 3-1.

The synchronous 1:1 bridge mode requires that the on-chip and off-chip AHB bus

clocks run at the same frequency. The bridge is only provided with the on-chip bus

clock. The maximum frequency of the on chip bus clock is restricted by the off-chip bus

timing. The paths between the slave and master interfaces of the bridge are registered

to provide timing isolation. Registering the AHB signals means that accesses through

the bridge incur delays.

The synchronous N:1 bridge mode requires that the on-chip bus clock to runs at an

integer multiple of the off-chip AHB bus clock. The bridge is provided with the on-chip

bus clock and a clock enable signal. The clock enable indicates which clock edges are

valid for the off-chip bus. The maximum frequency of each bus clock is restricted by the

timing for that bus and the requirement that the on-chip bus clock must run at an integer

multiple of the off-chip bus clock. The paths between the slave and master interfaces of

the bridge are registered to provide timing isolation. Registering the AHB signals means

that accesses through the bridge incur delays.

The asynchronous bridge mode allows the on-chip and off-chip AHB bus clocks to run

at completely independent frequencies. The bridge is provided with two clocks. The

maximum frequency of each bus clock is only restricted by the timing for that bus. The

paths between the slave and master interfaces of the bridge are registered in both clock

domains to provide timing isolation. The registering of the AHB signal paths in both

clock domains mean that the bridge will add several clock cycles delay to transactions.

The pass-through bridge mode requires that the on-chip and off-chip AHB bus clocks

to run at the same frequency. The bridge is only provided with the on-chip bus clock.

The maximum frequency of the on-chip AHB bus clock is limited by the timing of

signal paths off and on the chip. The paths between the slave and master interfaces of

Table 3-1 On-chip bridge selection

CFGAHBASYNC CFGHCLKEXTDIVSEL[2:0] CFGAHBPASST BRIDGESEL[1:0]

Bridge

selected

1xxx x00

Asynchronous

0 001-111 x 01

Synchronous

N:1

0000 010

Synchronous

1:1

0000 111

Pass-through