Specifications

Memory Map and Memory Configuration

The bridge AHB master output signals drive the pads of the chip through tristate buffers.

As the AHB read and write data buses are never active at the same time, the two are

combined onto one set of pads. Tristate buffers allow the write data bus to drive the

external AHB data bus. The action of the tristate buffers allows multiple AHB masters

to drive the off-chip AHB bus under the control of an external arbiter. The AHB arbiter

output signals do not use tristate buffers.

The bridge slave interface is part of the memory map and it will respond to transactions

in the appropriate address range. The address input of the slave interface is a full 32-bit

address, even though it responds to a decoded address range as it is passed through the

bridge unchanged. No address translation is performed. This links the on-chip and

off-chip AHB busses and preserves the on-chip address map.

Transactions initiated by the on-chip AHB masters are passed from the slave interface

to the master interface of the bridge. The response of off-chip peripherals is then passed

back through the bridge. The response of the bridge is dependent on the clock

arrangement between the two AHB busses and response of the off-chip peripheral. The

bridge will always ensure that AMBA AHB protocols are observed on both AHB

busses. To ensure this the slave interface can generate wait states and the master

interface can insert BUSY cycles.

A system design outside of the ARM926EJ-S Development Chip might break the AHB

protocol. If fixed length bursts are broken by an arbiter on the transfer source side of the

bridge, an incomplete burst appears on the destination side of the bridge. To avoid

breaking the AHB protocol, set the configuration signals CFGINCOVERRIDEM1

and CFGINCOVERRIDEM1 HIGH. All burst information will be converted to INCR.

If this situation cannot be encountered due to the system design, fixed length bursts can

be passed across the bridges (set CFGINCOVERRIDEM1 and

CFGINCOVERRIDEM1 LOW).

The bridge can operate in four modes that define the relationship between the on-chip

and off-chip AHB bus clocks and the response of the bridge to AHB transfers. These

modes are:

• Synchronous 1:1 bridge

• Synchronous N:1 bridge

• Asynchronous bridge

• Pass-through bridge.