Specifications

Memory Map and Memory Configuration

3.1.3 AHB restrictions

Using a multilayer AHB system requires that certain restrictions are placed on the use

of locked transfers to prevent a deadlock situation. A sequence of locked transfers must

all be performed to the same slave in the system. A bus master can ensure this restriction

is met by ensuring that a locked sequence of transfers remains inside a 1KB address

region.

Specifically, if a bus master is to perform two locked transfer sequences to different

address regions, the bus master must not start the second locked transfer sequence until

the final data phase of the first locked transfer sequence has completed.

3.1.4 AHB bus interfaces

This section describes the AHB bridges that forms part of the ARM926EJS PrimeXsys

Platform Development Chip multi-layer AHB system.

Off-chip (master) bridges

The off-chip AHB bridges are AMBA compliant bridges that allows AHB masters in

the ARM926EJ-S PXP subsystem to access off-chip AHB slave peripherals. The

off-chip AHB bridge has the following features:

• AMBA compliant AHB slave and master interfaces.

• Synchronous and asynchronous operation.

• Pass-through mode for cycle accurate modeling.

• Tristate pin control for multi-master AHB systems off-chip.

The block diagrams for the off-chip bus interfaces (M1 and M2) are shown in Figure 3-2

on page 3-7 and Figure 3-3 on page 3-8.