Specifications

Memory Map and Memory Configuration

The ARM926EJ-S PXP Slave Expansion AHB interfaces that are used have only one

peripheral connected to them and the ARM926EJ-S PXP Master Expansion AHB

interface has only one master connected to it. Consequently no additional AMBA

infrastructure components are required.

The ARM Instruction, DMAC 1, DMAC 2 and LCD AHB interfaces from the PXP

subsystem are unused. The ARM926EJ-S PXP memory map is modified in this

implementation so that no additional peripherals can be accessed via these interfaces.

The multi-layer interconnections are optimized to remove any redundant connections.

For instance, the CLCDC master is intended to fetch significant quantities of data from

memory devices. The CLCDC cannot usefully fetch data from communications

peripherals on the DMA APB bus. Therefore the DMA APB bridge is not connected as

a slave on the CLCDC AHB.

Arbitration between the buses only occurs when two or more masters try to gain access

to the same slave. The arbitration priority is fixed as:

1. CLCDC AHB (highest priority).

2. DMA0 AHB.

3. Expansion Master AHB

4. DMA1 AHB.

5. ARM Data AHB.

6. ARM Instruction AHB (lowest priority).

The slave arbitration is performed at the start of every transfer and on the quadword

boundary of any incrementing burst.

The ARM926EJ-S Development Chip adds four AHB peripherals into the

ARM926EJ-S PXP memory map:

• MBX Graphics Accelerator is mapped into a 16MB region at

0x40000000

• The AHB Monitor block is mapped into a 64KB region at

0x101D0000

• Off-chip AHB bridge 1 is mapped into a region defined by

CFGBRIDGEMEMMAP

• Off-chip AHB bridge 2 is mapped into a region defined by

CFGBRIDGEMEMMAP.