Specifications

Memory Map and Memory Configuration
3-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
Figure 3-1 Bus matrix configuration
System
Controller
(SP810)
Core
APB
GPIO x4
(PL061)
UART x3
(PL011)
SSP1
(PL022)
SCI
(PL131)
ARM926EJ-S
Dev. Chip
DMA
APB
Bus matrix
multiplexors
and decoders
AHB
Mon.
Bus
interface
Bus
interface
AHB/APB bridge
VIC
(PL190)
CLCDC
(PL110)
MPMC
(GX175)
MOVE
ETM9
AHB/APB bridge
Dual Timer
(SP804) x2
RTC
(PL031)
Watchdog
(SP805
MBX HR-S
accelerator
DMA0 AHB
EXP AHB
DMA1 AHB
CLCDC AHB
ARM Instruction AHB
ARM Data AHB
MBX interface port
ARM926EJ-S PXP
Subsystem
M
M
M
S
S
S
S
S
S
config S
S
S
S
S
M
M
M
AHB S
expansion
bus
AHB M1
expansion
bus
AHB M2
expansion
bus
MM
VFP9
config S
config S
config S
config S
SSMC
(PL093)
DMAC
(PL080)
S
SS
MM
Bus
interface
MS
JTAG
ARM926EJ-S