Specifications

Memory Map and Memory Configuration

Six AHB buses are provided:

ARM I AHB This bus is used by the instruction fetch port of the ARM926EJ-S

processor and has access to the memory interfaces. This AHB

supports external bus slaves.

ARM D AHB This bus is used by the data bus port of the ARM926EJ-S

processor and has access to all of the ARM926EJ-S Development

Chip peripherals. This AHB supports external bus slaves.

CLCDC AHB This bus is used by the ARM926EJ-S Development Chip CLCDC

to fetch display data from either of the memory interfaces. The

AHB supports external bus slaves.

DMA0 AHB This bus is used for DMA peripheral accesses and is connected to

the DMA APB bridge. External bus slaves are supported.

DMA1 AHB This bus is used for DMA memory accesses and is connected to

the memory interfaces. External bus slaves are supported.

Expansion AHB An expansion AHB bus supports the external M1 and M2 master

buses and the S slave bus.

Two Advanced Peripheral Buses (APBs) are provided. They are:

DMA APB This bus is used to access the APB peripherals that are required to support

DMA transfers. This APB supports external APB expansion with 11

external APB select lines provided.

Core APB This bus is used to access the APB peripherals that are required by the

ARM926EJ-S processor.

3.1.2 Bus matrix

TheARM926EJ-S Development Chip bus matrix is implemented in a single module. It

is constructed using two basic components:

Input stage This is used to request access to the required slave port and to

buffer the AHB address phase signals (for example, HADDR and

HTRANS) when access to the slave port is not granted.

Output stage This is used to arbitrate between the input stages that are

requesting access to the slave port.

The interconnect between the various input and output stages define the structure of the

bus matrix. For example, Figure 3-1 on page 3-4 shows the implementation of the

ARM926EJ-S Development Chip bus matrix.