Specifications

Memory Map and Memory Configuration

3.1 Overview of the AMBA buses in the ARM926EJ-S Development Chip

The ARM926EJ-S Development Chip bus architecture is described in the following

sections:

• About the bus architecture

• Bus matrix on page 3-3

• AHB restrictions on page 3-6.

Note

The bus system for the ARM926EJ-S Development Chip is highly configurable. This

enables the chip to emulate many different system designs, but it also complicates

configuration and use. The main areas of bus use that require attention are:

• selecting the physical memory that is accessed at

0x0

after a reset

• handling accesses to undefined areas that are remapped to external buses

• enabling the static controller for static memory

• recognizing that some buses cannot access devices located on a different bus

• identifying bus masters that can access different memory regions in parallel.

For a production device based on the ARM926EJ-S, most of these issues would be

resolved before the device was designed. However, many of these design choices must

be handled by program design or configuration settings in ARM926EJ-S Development

Chip the because it was produced for use in a development environment.

For more details on signals related to bus access, see the following manuals:

• ARM926EJ-S PrimeXSys Virtual Component Technical Reference Manual

• ARM926EJ-S Integration Guide

• AMBA Specification

• AMBA Design Kit Technical Reference Manual

• AHB EASY Technical Reference Manual

3.1.1 About the bus architecture

The ARM926EJ-S Development Chip peripherals are interconnected to enable

maximum flexibility in the final SoC performance by extensive use of multilayer

Advanced High-performance Bus (AHB). The multilayer AHB architecture provides a

performance advantage by enabling multiple bus masters to be active in parallel. For

example, the DMAC can transfer data to the UART, while the CLCDC fetches data from

the MPMC and the ARM processor accesses the Timer modules.