Specifications

System Controller and Configuration Logic

Table 2-8 lists the JTAG signals.

MPMCCLK[4:0] Output These are the output clocks from the MPMC.

SMCLK[2:0] Output These are the output clocks from the SSMC.

SMFBCLK Input This input is the feedback clock for the SSMC.

Table 2-7 Clock signals (continued)

Clock Direction Description

Table 2-8 JTAG TAP signals

Signal Name Type Description

TCK Input Test clock.

TMS Input Test mode select.

nTRST Input Test reset (active LOW).

TDI Input Boundary scan input.

nBSTAPEN Input When LOW the boundary scan TAP controller is selected. When HIGH the

Multi-ICE processor debug interface is selected.

TDO Tristate output Boundary scan output.

RTCK Output Mullet-ICE TCK synchronization.