Specifications
System Controller and Configuration Logic
2-32 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
Table 2-7 lists the clock signals.
Table 2-7 Clock signals
Clock Direction Description
XTALCLKEXT Input If the on-chip PLL is used, this input is the reference clock for the PLL.
If the on-chip PLL is not used, this input can drive the processor and AMBA
subsystem clocks. This clock can be selected from the System Controller.
PLLCLKEXT Input If the on-chip PLL is not used, this input can drive the processor and AMBA
subsystem clocks. This clock can be selected from the System Controller
HCLKM1 Input This input provides an alternative clock source that can be used to time the
external part of the M1 bus.
HCLKM2 Input This input provides an alternative clock source that can be used to time the
external part of the M2 bus.
HCLKS Input This input provides an alternative clock source that can be used to time the
external part of the S bus.
CLCDCLKEXT Input This input is used to drive the external interface of the CLCDC.
REFCLK32K Input This input provides a constantly running slow frequency used to provide a
timing reference for the Timer and Watchdog modules at a nominal rate of
32kHz (32768Hz).
RTC1HZCLK Input This input is used to clock the RTC timer at a nominal rate of 1Hz.
SCIREFCLKEXT Input This input is used to drive the external interface of the SCI.
SSPCLKEXT Input This input is the clock for the SSP external interface.
TIMCLKEXT Input This input provides an alternative clock source that can be used by the
ARM926EJ-S Development Chip Timer modules. It must remain constant
when the PLL frequency is varied. It is required to provide the Timer modules
with at least 10µs resolution and must therefore be at least 100KHz although
much higher frequencies can also be used.
UARTCLKEXT Input This input provides an alternative clock source that can be used to derive the
UART baud frequencies.
nPLLRESET Input On-chip PLL reset (active LOW).
PLLPWRDN Input On-chip PLL power down (active HIGH).
TCK Input This input is the JTAG clock
RTCK Output This output is the returned JTAG clock