Specifications

System Controller and Configuration Logic

Table 2-6 lists the reset and configuration signals.

Table 2-6 Reset and configuration signals

Signal Name Type Description

nPORESET Input This is an active-LOW power-on reset input used to reset the MPMC

refresh timer, System Controller, and the Clock and Reset Controller.

CONFIGDATA[28:0] Inputs Configuration inputs on HDATAM2[28:0] sampled at reconfiguration.

(See External configuration signals on page 2-19 for details.)

nCONFIGCLR Input This resets all of the configuration bits before nPORESET and

nRESET are released.

CONFIGINIT Input Samples the status of pads to define the configuration signals (rising

edge).

nRESET Input System reset (active LOW).

TESTSELECT Input Manufacturing test mode select. This signal is asynchronous and should

be static after reset. Signals form the Configuration block and the Clock

and Reset Controller are forced to a known state.

Note

This signal is used for manufacturing test only and must always be held

LOW.

SCANENABLE Input Manufacturing test mode scan enable.

Note

This signal is used for manufacturing test only.

BIGENDOUT Output Byte endian mode.