Specifications

System Controller and Configuration Logic

2.6 Control, configuration, and test signals on pads

This section lists control, configuration, and test signals on the input/output pads.

Note

For details on AHB signals, see Chapter 3 Memory Map and Memory Configuration

and Chapter 4 AHB Monitor.

For details on other peripherals and controllers, see the chapter describing the

component.

In order to simplify finding signal information, some signals appear in more than one

table. For example TCK is in both Table 2-7 on page 2-32 and Table 2-8 on page 2-33.

Table 2-4 lists the debug signals for the ARM926EJ-S.

Table 2-5 lists the ETM signals.

Table 2-4 ARM926EJ-S signals

Signal

Name

Type Description

DBGACK Output Debug acknowledge indicates when the ARM CPU is in

debug state (active HIGH).

EDBGRQ Input External request for ARM to enter debug state (active

HIGH).

Table 2-5 ETM signals

Signal Name Type Description

ETMEXTIN Input Debug cross trigger support.

ETMEXTOUT[3:0] Output Debug cross trigger support.

PIPESTAT[2:0] Output Pipeline status

TRACECLK Output Trace clock

TRACEPKT[15:0] Output Trace packet port

TRACESYNC Output Trace synchronization