Specifications

System Controller and Configuration Logic
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-25
2.4 JTAG logic
The JTAG interface can control one of two TAP controllers. When nBSTAPEN is LOW
the boundary scan TAP controller is selected. The boundary scan TAP controller is a
Synopsys DesignWare component. When nBSTAPEN is HIGH the ARM926EJ-S
processor TAP controller is selected. This is part of the ARM926EJ-S processor debug
features.
The ARM926EJ-S processor TAP controller runs at core clock frequency and so some
signals must pass through a Multi-ICE Synchronization block. A return clock RTCK is
provided to indicate when TDO is valid.
Figure 2-7 on page 2-26 shows how the JTAG interface is connected to the boundary
scan TAP controller and ARM926EJ-S processor.
Note
There are Pull-ups on input pins nTRST, TDI and TMS.
Figure 2-8 on page 2-27 shows how the Multi-ICE synchronization registers are
inserted between the JTAG test access port and the ARM926EJ-S processor.