Specifications

System Controller and Configuration Logic
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-23
CFGAHBSASYNC On-chip AHB bridge and clock
and reset controller
Force the on-chip bridge to asynchronous mode
(active HIGH).
The reset value is
0 . A new value is loaded from
HDATAM2[24] during reconfiguration.
CFGAHBPASST All AHB bridges Switch the off-chip and on-chip bridges to
pass-through mode (active HIGH).
The reset value is 0 . A new value is loaded from
HDATAM2[25] during reconfiguration.
CFGINCROVERRIDEM1 Off-chip AHB bridge 1 Override burst transfer with INCR mode (active
HIGH).
The reset value is 0 . A new value is loaded from
HDATAM2[26] during reconfiguration.
CFGINCROVERRIDEM2 Off-chip AHB bridge 2 Override burst transfer with INCR mode (active
HIGH).
The reset value is 0 . A new value is loaded from
HDATAM2[27] during reconfiguration.
CFGINCROVERRIDES On-chip AHB bridge Override burst transfer with INCR mode (active
HIGH).
The reset value is 0 . A new value is loaded from
HDATAM2[28] during reconfiguration.
Table 2-3 Configuration signal destinations (continued)
Signal name Destination Description