Specifications

System Controller and Configuration Logic
2-22 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
CFGHCLKEXTDIVSEL[2:0] Clock and reset controller Sets the HCLK to HCLKEXT divide ratio. The
divide value is set as follows:
b000 = 1
b001 = 2
b010 = 3
b011 = 4
b100 = 5
b101 = 6
b110 = 7
b111 = 8.
The reset value is b001 . A new value is loaded
from HDATAM2[17:15] during
reconfiguration.
CFGMBXCLKDIVSEL[1:0] MBX Graphics Accelerator,
CLKRATIO[1:0]
Sets the HCLK to MBXCLK divide ratio. The
divide value is set as follows:
b00 = 1
b01 = 2
b10 = 3
b11 = 4.
The reset value is b01 . A new value is loaded
from HDATAM2[19:18] during
reconfiguration.
CFGSMCCLKDIVSEL[1:0] SSMC,
SMMEMCLKRATIO[1:0]
Sets the HCLK to SMCLK divide ratio for
SSMC. The divide value is set as follows:
b00 = 1
b01 = 2
b10 = 3
b11 = 4.
The reset value is b01 . A new value is loaded
from HDATAM2[21:20] during
reconfiguration.
CFGAHBM1ASYNC Off-chip AHB bridge 1 and
clock and reset controller
Force off-chip bridge 1 to asynchronous mode
(active HIGH).
The reset value is 0 . A new value is loaded from
HDATAM2[22] during reconfiguration.
CFGAHBM2ASYNC Off-chip AHB bridge 2 and
clock and reset controller
Force off-chip bridge 2 to asynchronous mode
(active HIGH).
The reset value is 0 . A new value is loaded from
HDATAM2[23] during reconfiguration.
Table 2-3 Configuration signal destinations (continued)
Signal name Destination Description