Specifications

System Controller and Configuration Logic

CFGREMAPDYEXEN ARM926EJ-S Development

Chip AMBA infrastructure

Dynamic memory and expansion memory alias

enable.

When HIGH and CFGREMAPSTEXEN is

HIGH, then expansion memory is aliased to

0x00000000

Note

The combination of CFGREMAPDYEXEN

HIGH and CFGREMAPSTEXEN LOW is

reserved and must not be used.

The reset value is 0. A new value is loaded from

HDATAM2[5] during reconfiguration.

CFGBRIDGEMEMMAP ARM926EJ-S Development

Chip AMBA infrastructure

Select memory map for the off-chip bridges.

The reset value is 1. A new value is loaded from

HDATAM2[6] during reconfiguration.

CFGUSEPLL Clock and reset controller Uses the on-chip PLL to drive the processor and

AMBA subsystem (active HIGH).

The reset value is

. A new value is loaded from

HDATAM2[10] during reconfiguration.

CFGPLLBYPASS Clock and reset controller Forces the PLL output to be bypassed (active

HIGH).

The reset value is

. A new value is loaded from

HDATAM2[11] during reconfiguration.

CFGPLLSHORTFB Clock and reset controller Removes the clock tree delay from the PLL

feedback (active HIGH).

The reset value is

. A new value is loaded from

HDATAM2[12] during reconfiguration.

CFGHCLKDIVSEL[1:0] Clock and reset controller Sets the CLK to HCLK divide ratio. The divide

value is set as follows:

b00 = 1

b01 = 2

b10 = 3

b11 = 4.

The reset value is

b01

. A new value is loaded

from HDATAM2[14:13] during

reconfiguration.

Table 2-3 Configuration signal destinations (continued)

Signal name Destination Description