Specifications

System Controller and Configuration Logic
2-20 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
Table 2-3 Configuration signal destinations
Signal name Destination Description
CFGCPUVINITHI ARM926EJ-S processor
VINITHI
Determines the reset location of the exception
vectors for the ARM926EJ-S processor.When
LOW, the vectors are located at
0x0000000 .
When HIGH, the vectors are located at
0xFFFF0000 .
The reset value is
0 . The value is loaded from
HDATAM2[0] during reconfiguration.
CFGCPUBIGENDIN ARM926EJ-S processor
BIGENDINIT
Defines the byte endian mode at reset. When
LOW, little endianness is used. When HIGH,
big endianness is used.
The reset value is 0 . The value is loaded from
HDATAM2[1] during reconfiguration.
CFGVFPENABLE Clock and reset controller and
coprocessor multiplexor.
VFP9-S coprocessor enable (active HIGH).
The reset value is 1 . The value is loaded from
HDATAM2[2] during reconfiguration.
CFGMPMCnSMC ARM926EJ-S Development
Chip AMBA infrastructure
MPMCnSMC
Defines which static memory controller is used.
When LOW, the SMC is used. When HIGH, the
MPMC is used.
The reset value is 0 . The value is loaded from
HDATAM2[3] during reconfiguration.
CFGREMAPSTEXEN ARM926EJ-S Development
Chip AMBA infrastructure.
Static memory and expansion memory alias
enable.
When HIGH and CFGREMAPDYEXEN is
LOW, then static memory is aliased to
0x00000000 .
When HIGH and CFGREMAPDYEXEN is
HIGH, then expansion memory is aliased to
0x00000000 .
The reset value is 1. The value is loaded from
HDATAM2[4] during reconfiguration.