Specifications

System Controller and Configuration Logic

2.3 External configuration signals

The configuration block is used to define the operating mode of the chip. It samples the

state of HDATAM2[28:0] pads while the rest of the chip is held in reset. The state of

these pads can then be held to drive configuration signals within the chip. The operating

mode of the chip is then defined when reset is released.

Note

In a typical device, the configuration signals would be tied HIGH or LOW. The

configuration signals are brought out of the chip to allow different system settings to be

tested with the ARM926EJ-S Development Chip.

The configuration block reset nCONFIGRST and clock CONFIGINIT are

independent of the rest of the chip. While the chip is held in reset the configuration

block can be reset and sample the input data CONFIGDATA[28:0] to set the mode of

the chip. The chip can then be released from reset and operate in the defined mode. The

reset state of the configuration signals defines a default mode that can be used instead

of sampling pads on reset.

See Table 2-2 for the source of the configuration signals and Table 2-3 on page 2-20 for

the destination of the configuration signals.

Table 2-2 Configuration signal sources

Signal name Source Description

CONFIGDATA[28:0] HDATAM2[28:0] Configuration signals from data bus

pads.

nCONFIGCLR Clock and reset controller Force all configuration signals to

reset state (active LOW).

CONFIGINIT Clock and reset controller Sample status of pads on rising edge.