Specifications

System Controller and Configuration Logic
2-18 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
2.2.3 Peripheral clock selection
The external clock signals are user-defined off-chip clocks. They are gated by the
System Controller outputs PERIPHCLKENx. Alternatively, the peripheral clocks may
be derived from HCLK.
In normal operation the System Controller output PERIPHCTRL0x selects the clock
source. To ensure correct operation of the peripheral PERIPHCTRL0x should not
change state while the gate is enabled. At reset the PERIPHCTRL0x outputs are set
low by the system controller, therefore selecting the External Clocks.
Table 2-1 External peripheral clocks and clock control signals
External Clock
Peripheral
Clock
PERIPHCLKENx and
PERIPHCLKSTATx
PERIPHCTRL0x
CLCDCLKEXTIN CLCDCLK 33
SSPCLKEXTIN SSPCLK 44
SCIREFCLKEXTIN SCIREFCLK 55
UARTCLKEXTIN UARTCLK0 66
UARTCLKEXTIN UARTCLK1 77
UARTCLKEXTIN UARTCLK2 88