Specifications

System Controller and Configuration Logic

2.2.2 SDRAM interaction with frequency and power modes

The SDRAM refresh period is programmed into the MPMC in HCLK tick units. This

setting must be reprogrammed when the operating frequency of the ARM926EJ-S

Development Chip changes (when the PLL frequency control is altered or if the system

switched operating mode between NORMAL or SLOW). When moving to:

• a higher HCLK frequency the refresh period must be updated after the transition

•a lower HCLK frequency the refresh period must be updated before the transition

to a setting suitable for the target operating frequency.

Before entering operating modes where the HCLK frequency is very low or stalled

(DOZE and SLEEP modes) the SDRAM must be put into self-refresh mode. In this

mode the SDRAM is not accessible.

Note

Other peripherals, such as the SCI, must have the correct shutdown sequence applied

before the system can be put into the DOZE or SLEEP mode.

Note

The feedback clock to the MPMC and SSMC are input to the clock selection and gating

block shown in Figure 2-4 on page 2-13. MPMCFBCLK[3:0] and SMFBCLK[3:0]

are only buffered in this block.