Specifications

System Controller and Configuration Logic

In the example shown in Figure 2-5 on page 2-14 and with the default clock and

configuration values:

• The 24MHz oscillator provides the XTALCLKEXT input clock for the PLL in

the ARM926EJ-S Development Chip.

• The PLL output CPUCLK is used as the CPU core clock and as the input to the

HCLK divider.

• HCLK is CPUCLK divided by 1, 2, 3, or 4 depending on the value of

CFGHCLKDIVSEL[1:0]. HCLK is used as the SDRAM clock MPMCCLK,

and as the inputs to the MBX and SMC clock dividers.

• HCLKEXT is HCLK divided by 1 to 8 depending on the value of

CFGHCLKEXTDIVSEL[2:0]. HCLKEXT is the reference clock for the

external part of the AMBA bridges M1, M2, and S. This clock is the feedback

clock for the PLL, therefore the frequency of HCLKEXT is the same as that of

XTALCLKEXT.

The system controller in the ARM926EJ-S Development Chip can switch the system

into power-saving modes (slow, doze, and sleep).

In the power-saving modes, the external low-frequency clocks are used as CPUCLK.

Because of the low-speed external clock, the AHB bridges typically operate in the lower

performance asynchronous mode and are controlled by external clocks HCLKM1,

HCLKM2, and HCLKS.

The following signals control the internal multiplexors in the ARM926EJ-S

Development Chip:

CFGPLLBYPASS Bypasses the PLL and uses XTALCLKEXT as the input to the

CPUCLK multiplexor. The default is LOW, the PLL output is

used.

CFGUSEPLL Selects an external clock (REFCLK32K, PLLCLKEXT, or

XTALCLKEXT) instead of the PLL output as CPUCLK. The

default is HIGH, the output from the PLL multiplexor is used and

the power-saving modes are disabled.