Specifications

System Controller and Configuration Logic

The clock and reset controller has two modes of operation for driving the processor

clocks:

• Use the on-chip PLL to de-skew on-chip clocks with respect to the off-chip

reference clock XTALCLKEXT.

• Drive the on-chip CPUCLK master clock from one of three asynchronous

off-chip clocks: REFCLK32K, PLLCLKEXT, or XTALCLKEXT.

The clock and reset controller generates two clocks for the AHB bridges:

• The internal HCLK is always used to control the internal side of the AHB

bridges.

HCLK is also used to clock the external part of the bridges for synchronous 1:1

operating mode.

• The external part of the three AHB bridges can be driven by HCLKEXT in

synchronous mode if the clock ratio is not 1:1.

The external part of the three AHB bridges can also be driven by an external clock

(HCLKM1 for master 1, HCLKM2 for master 2, or HCLKS for the slave bus) for

asynchronous operating mode.

All ARM926EJ-S Development Chip clocks, except for the System Controller clock

itself (SCLK), are turned off in SLEEP mode.

Using the PLL to de-skew the on-chip clocks with respect to XTALCLKEXT allows

synchronous AHB bridges to be used for low latency data transfer across the chip

boundary. The XTALCLKEXT frequency must meet the minimum PLL input

frequency requirement. The PLL also multiplies XTALCLKEXT to allow the

processor clock and AMBA subsystem clocks to be at higher frequencies. As the PLL

is the only source of clocks for the processor and AMBA subsystem the frequency

cannot be changed during normal operation. The clock ratio between the processor,

AMBA subsystem and XTALCLKEXT is fixed after reset. Changes in the System

Controller state machine have no affect on the clocks though it can still move through

the power management states and application software will be unaffected.

Driving the on-chip clocks from one of three asynchronous off-chip clocks

(REFCLK32K, PLLCLKEXT, or XTALCLKEXT) allows the System Controller

state machine to select the clock source. The System Controller can switch between

clocks running at different speeds as part of a power management strategy. It can also

change the processor to AMBA subsystem clock ratio. The on-chip PLL cannot be used

to de-skew clocks as the input frequencies may be outside of the PLL specification. The

skew between on-chip and off-chip clocks requires asynchronous AHB bridges to be

used. The data transfer latency of asynchronous bridges is much higher than that of the

synchronous bridges.