Specifications

System Controller and Configuration Logic

Core clock control

To enable the software to control the relative frequency of the core clock, CLK, and the

bus clock, HCLK, the System Controller provides access to the HCLKDIVSEL[2:0]

output through the system control register. These output signals are intended for use by

the clock generation logic to control the generation of the CLK/HCLK clock source

and the HCLKEN input.

To prevent spurious changes of the CLK/HCLK clock ratio, the HCLKDIVSEL

output can only change when the system mode control state machine is in a stable state.

That is, the actual system mode matches the required system mode.

HCLK to CLK relationship

HCLK and CLK are synchronous. In a very simple clock generation case, HCLK and

CLK can be tied together and then HCLKEN is tied HIGH. This means that there is a

1:1 relationship between the CPU core clock and the bus clock HCLK.

Using this configuration limits the frequency that the core can run at to the maximum

frequency supported by HCLK. To use the higher operating frequency capability of the

core, CLK must operate at a multiple of the HCLK frequency. Configuration of this is

supported by the system control register. HCLK can be set as equal to, divided by two,

divided by three, or divided by four of CLK. This configuration is independent of

operating mode. However, modes other than NORMAL only ever have to use 1:1.