Specifications

System Controller and Configuration Logic

PLL control transition state, PLL CTL

PLL control transition state is used to initialize the PLL. In this mode both the systems

clock and the System Controller clock are driven from the output of the crystal

oscillator.

The system moves into the Switch to PLL transition state when either:

• the PLL timeout define in the PLL control register expires (when the

PLLTIMEEN input is valid)

• the PLLON input is set to logic 1.

Switch to PLL transition state, SW TO PLL

Switch to PLL transition state is used to initiate the switching of the system clock source

from the crystal oscillator to the PLL output.

The system moves into the NORMAL mode when the PLLSW input is set to a logic 1,

to indicate that clock switching is complete.

Switch from PLL transition state, SW FROM PLL

Switch from PLL transition state is entered when moving from the NORMAL mode to

SLOW mode. It initiates the switching of the clock sources from the PLL to the crystal

oscillator output.

The system moves into the SLOW mode when the PLLSW input is reset to a logic 0,

to indicate that clock switching is complete.

NORMAL mode

In NORMAL mode both of the system clocks and the System Controller clock are

driven from the output of the PLL.

If the NORMAL mode control bit is not set the system moves into the Switch from PLL

transition state.