Specifications

System Controller and Configuration Logic

It is possible to override the mode control bits (in the system control register) when an

interrupt is generated by the VIC, see Interrupt response mode on page 2-3. The state

transitions are shown in Figure 2-3 on page 2-8.

The signal states that are required to achieve the modes and transitions shown in

Figure 2-3 on page 2-8 are listed in Table 2-1.

SLEEP mode

In SLEEP mode, the system clocks, HCLK and CLK, are disabled and the System

Controller clock, SCLK, is driven from a slow speed oscillator (nominally 32768Hz).

When either a FIQ or an IRQ interrupt is activated (through the VIC) the system moves

into the DOZE mode. Additionally, the required operating mode in the system control

Note

Before entering SLEEP mode you must ensure that the processor is in the

Wait-for-interrupt state. Processor status is determined by the STANDBYWFI output

from the processor.

Table 2-1 System mode control signal states

Transition/mode

Signal

XTALEN XTALRQSW PLLEN PLLRQSW SLEEPMODE

NORMAL 1 1 1 1 0

SW from PLL 1 1 1 0 0

SW to PLL 1 1 1 1 0

PLL CTL 1 1 1 0 0

SLOW 1 1 0 0 0

SW from XTAL 1 0 0 0 0

SW to XTAL 1 1 0 0 0

XTAL CTL 1 0 0 0 0

DOZE 0 0 0 0 0

SLEEP 0 0 0 0 1