Specifications

System Controller and Configuration Logic
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-7
2.1.8 System mode control
A system mode control state machine is provided to define the source of the system
clock and System Controller clock inputs.
Note
Most applications only use NORMAL mode. The other modes are used for special
power down conditions.
The state machine is controlled using three mode control bits in the system control
register, which define the required system operating mode. The modes are controlled by
the mode control bits:
1xx If the Most Significant Bit (MSB) is set then the system moves into
NORMAL mode.
01x If the MSB is not set and the next MSB is set then the system
moves into SLOW mode. This is described in SLOW mode on
page 2-10.
001 If only the Least Significant Bit (LSB) is set then the system
moves into DOZE mode. This is described in DOZE mode on
page 2-10.
000 If none of the mode control bits are set the system moves into
SLEEP mode. This is described in SLEEP mode on page 2-9.
Note
x denotes that the bit can be set to 0 or 1.
When the required operating mode has been defined in the system mode control register
the system mode control state machine moves to the required operating mode without
further software interaction.
The current system mode is output on the SYSMODE[3:0] bus and can also be read
back by the processor using the ModeStatus bit in the SCCTRL Register.
Following a power-on reset the system mode control state machine enters DOZE mode.
Note
It is the responsibility of the system integrator to ensure that all the required clock
sources are active and stable before the power-on reset is released and system operation
begins.