Specifications

System Controller and Configuration Logic
2-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
The Watchdog module enable is generated from the REFCLK input and a single
WDOGCLKEN pulse is generated on every rising edge of REFCLK.
The Timer module enable can be selectively generated from either the REFCLK or
TIMCLK inputs. This is shown for WDOGCLKEN and TIMER1CLKEN in
Figure 2-2.
Figure 2-2 Reference frequency select for Watchdog and Timer modules clock enable
To support debugging the system software, both Timer and Watchdog modules stall
when the ARM processor is in Debug mode.
2.1.7 PLL frequency control
The PLL frequency control register is provided (SCPLLFCTRL). is not used in the
ARM926EJ-S Development Chip.