Specifications

System Controller and Configuration Logic

Figure 2-1 Enable signal generation for the Timer and Watchdog modules

The module enable signals are:

• WDOGCLKEN for the Watchdog module

• TIMERCLKEN0 for timer clock enable 0

• TIMERCLKEN1 for timer clock enable 1

• TIMERCLKEN2 for timer clock enable 2

• TIMERCLKEN3 for timer clock enable 3.

The enable signal for the Watchdog module is generated from the REFCLK input.

The Timer module enable signals are selectively generated as defined in the System

Control Register from either:

• REFCLK

• TIMCLK.

Additionally, to enable the Watchdog and Timer modules to be clocked directly at the

system clock rate, it is also possible to selectively force the enable outputs HIGH.

The watchdog clock enable output can be forced inactive by deasserting the WDEN

input. For example, the WDEN input can be used to disable the watchdog timer when

the processor core is in a debug state.

Watchdog and Timer modules clock enable generation

The Watchdog and Timer modules have clock enable terms generated synchronously to

CLK by the System Controller:

• WDOGCLKEN

• TIMER1CLKEN

• TIMER2CLKEN

• TIMER3CLKEN

• TIMER4CLKEN.

To enable the Timer and Watchdog module enable signals to be generated at a constant

rate independently of the system clock, the signals are derived from asynchronous,

fixed-rate clock inputs.