Specifications

System Controller and Configuration Logic

2.1.4 Low battery handling

Two inputs are provided to the ARM926EJ-S Development Chip to facilitate software

implementation of low battery and emergency power failure situations. These are:

BATOK This input is an alternate function of GPIO3[7] and tells the software that

there is sufficient charge in the battery for normal operation. When this

input is inactive the system must not move into an operating mode that

requires higher power consumption.

See the ARM PrimeCell GPIO (PL061) Technical Reference Manual for

details on enabling alternate functions.

PWRFAIL This primary input to the interrupt controller signals an emergency power

failure. Software must respond immediately by:

• switching off any high power consumption peripherals, such as

LCD back lights and displays

• moving the system from NORMAL to SLOW mode

• storing important application state

• placing the system into SLEEP mode.

The ARM926EJ-S Development Chip does not implement hardware to facilitate the

above functions. It is the responsibility of software to check the BATOK input before

raising the systems power consumption.

Software must also handle the PWRFAIL interrupt correctly.

2.1.5 System controller registers

The system controller registers start at memory location

0x101E0000

For detailed information on the System Controller registers, see the ARM PrimeCell

System Controller (SP810) Technical Reference Manual.

2.1.6 Watchdog and Timer module clock enable generation

Enable signals are generated to enable the Timer and Watchdog modules to be clocked

at a rate that is independent of the system clock. The enable signals are generated by

sampling a free-running, constant frequency clock from the TIMCLKEXT input and

generating an active HIGH pulse for a single SCLK clock cycle on each rising edge of

the input clock. This is shown in Figure 2-1 on page 2-5.