Specifications

Introduction

Default memory map

The default memory map is divided into the regions shown in Figure 1-3 on page 1-12.

They are configured as follows:

• SDRAM for CS0 and 1 are mapped into a 256Mb region starting at

0x00000000

• SDRAM for CS2 and 3 are mapped into a 256Mb region starting at

0x70000000

• the first set of four SSMC banks for CS4, CS5, CS6, and CS7 are mapped into a

256Mb region starting at

0x20000000

• the second set of four SSMC banks for CS0, CS1, CS2, and CS3 are mapped into

a 256Mb region starting at

0x30000000

The remaining peripheral interfaces are contained in a single 1Mb region, with the AHB

peripherals at the bottom of the region and the APB peripherals at the top. This enables

either type of peripheral to be added to the region.

Note

The remainder of the address map is decoded by an off-chip AHB bridge and is

provided for peripherals external to the ARM926EJ-S Development Chip. Because

these address regions are not decoded in the ARM926EJ-S Development Chip, valid

AHB responses must be generated through the external AHB interfaces to any access to

an undefined address region.

See Chapter 3 Memory Map and Memory Configuration for more information on the

AHB buses and the memory map.