Specifications

Introduction

1.3.1 External memory support

Two memory interfaces are provided to support external static memory and external

SDRAM. When modeling high-performance systems, both memory interfaces can be

used in parallel. In this configuration, the Synchronous Static Memory Controller

PrimeCell PL093 drives the static memory interface and the Multiport Memory

Controller PrimeCell GX175 drives the SDRAM memory interface.

When modeling a relatively low-performance system, one memory interface can be

used. In this configuration, the Multiport Memory Controller PrimeCell GX175 drives

both the static memory and the SDRAM memory interfaces.

The MPMC supports seven ports:

• six 32-bit ports (one port is dedicated to the MBX accelerator)

• a single 32-bit AHB configuration port.

The mapping between the ARM926EJ-S Development Chip AHB buses and the

MPMC ports is listed in Table 1-1.

The SSMC is not a multiport device. However, the AHB bus switch selects one of the

following buses for the SSMC:

• ARM Data AHB

• ARM Instruction AHB

•DMA1 AHB

• EXPM AHB expansion bus

The MPMC and SSMC have additional AHB control ports that are used to access the

configuration registers. These ports are only accessible using the ARM Data AHB bus.

Table 1-1 MPMC port allocation

ARM926EJ-S Development Chip

AHB

MPMC port

CLCDC AHB (highest priority) Port 0

EXPM AHB Port 1

DMA1 AHB Port 2

ARM Data AHB Port 3

ARM Instruction AHB Port 4

MBX Port 5