Specifications

Index
Index-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
pin numbering B-2
SSMC 1-5
features 13-2
I/O connections 13-5
pad signals 13-9, A-1
SSP
Features 14-2
Interrupts 14-5
pad signals 14-6
timing C-5
Static memory devices supported 10-5
Support code
IEEE 754 standard compliance 18-2
RunFast mode 18-2, 18-8
subnormal input 18-6
Supported dynamic memory devices
10-4
SynchFlash devices 10-4
System controller 1-5
core clock control 2-12
HCLK to CLK relationship 2-12
interrupt response mode 2-3
low battery handling 2-4
modes 2-7
operation 2-13
pad signals 2-30
PLL transition state 2-11
reset control 2-2
state machine 2-8
wait for interrupt control 2-3
Watchdog and Timer modules clock
generation 2-5
XTAL transition state
2-10
T
Timer
about 15-2
clock generation 2-4
mode 15-5
modules 1-6
overview 15-3
programmable parameters 15-5
registers 15-2
U
UART
features 16-2
FIFO 16-3
masking 16-3
pad signals 16-8
Reserved locations 16-5
16C550 16-7
V
Vectored interrupt 17-3, 17-9
VFP9
architecture 18-2
double-precision instructions 18-2
float-to-integer conversion 18-7
full-compliance mode 18-6
high-level language support 18-2
RunFast mode 18-8
VFP9 support code
full-compliance mode 18-6
RunFast mode 18-7
source data registers 18-4
subnormal input 18-6
user trap handler 18-7
VIC 1-6, 17-2
introduction 17-2
pad signals 17-11
W
Watchdog 1-7
base address 19-4
clock generation 2-4, 2-5
features 19-2
Windows CE software format 5-14